ADIN2111CCPZ-R7 datasheet(107/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 107 of 129

Table 196. Bit Descriptions for AN_LP_ADV_ABILITY_M (Continued)

Bits

Bit Name

Description

Reset

Access

AN_LP_ADV_MST

Link Partner Master/Slave Configuration. This bit reports the master/slave configuration of the

link partner, as follows: 0: slave, 1: master. See also the AN_LP_ADV_FORCE_MS bit, which

determines whether this bit expresses a preference or a forced value. See IEEE Standard 802.3

Subclause 98.2.1.2.3 (master/slave configuration is Bit 4 of the transmitted nonce field).

0x0

[3:0]

RESERVED

Reserved.

0x0

BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[47:32]

Device Address: 0x07; Register Address: 0x0207, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_H

This address corresponds to the BASE-T1 autonegotiation base page ability register, Bits[47:32], of the link partner specified in Clause

45.2.7.22 of Standard 802.3. Note that the value of this register is latched when AN_LP_ADV_ABILITY_L is read. Reading this register returns

the latched value rather than the current value.

Table 197. Bit Descriptions for AN_LP_ADV_ABILITY_H

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

AN_LP_ADV_B10L_EEE

Link Partner 10BASE-T1L EEE Ability. This bit reports if the link partner is

capable of using 10BASE-T1L energy efficient Ethernet.

0x0

AN_LP_ADV_B10L_TX_LVL_HI_ABL

Link Partner 10BASE-T1L High Level Transmit Operating Mode Ability.

This bit reports whether the link partner is capable of transmitting in the

high level (2.4 V p-p) transmit operating mode. This bit is used with

AN_LP_ADV_B10L_TX_LVL_HI_REQ to configure the 10BASE-T1L transmis-

sion level (2.4 V p-p or 1.0 V p-p); see the AN_ADV_B10L_TX_LVL_HI_REQ

bit for more details.

0x0

AN_LP_ADV_B10L_TX_LVL_HI_REQ

Link Partner 10BASE-T1L High Level Transmit Operating Mode Request. This

bit reports whether the link partner is requesting that the high level (2.4 V p-p)

transmit operating mode be used. See the AN_ADV_B10L_TX_LVL_HI_REQ

bit for more details.

0x0

AN_LP_ADV_B10S_HD

Link Partner 10BASE-T1S Half-Duplex Ability. This bit reports if the link partner

is capable of using 10BASE-T1S half duplex.

0x0

[10:0]

RESERVED

Reserved.

0x0

BASE-T1 Autonegotiation Next Page Transmit Register, Bits[15:0]

Device Address: 0x07; Register Address: 0x0208, Reset: 0x2001, Name: AN_NEXT_PAGE_L

This address corresponds to the BASE-T1 autonegotiation next page transmit register, Bits[15:0], specified in Clause 45.2.7.23 of Standard

802.3. On power-up or autonegotiation reset, this register contains the default value, which represents a message page with the message code

set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L.

Table 198. Bit Descriptions for AN_NEXT_PAGE_L

Bits

Bit Name

Description

Reset

Access

AN_NP_NEXT_PAGE_REQ

Next Page Request. This bit indicates to the link partner that the PHY wants to send a next

page. See IEEE Standard 802.3 Subclause 98.2.1.2.9.

0x0

R/W

AN_NP_ACK

Next Page Acknowledge. See IEEE Standard 802.3 Subclause 98.2.1.2.8.

0x0

AN_NP_MESSAGE_PAGE

Next Page Encoding. Indicates encoding of next page, as follows:

0x1

R/W

0: unformatted next page.

1: message next page.

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