ADIN2111CCPZ-R7 datasheet(74/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 74 of 129

Seconds Counter Register

Address: 0x82, Reset: 0x00000000, Name: TS_SEC_CNT

Use this register to write to the seconds counter.

Table 86. Bit Descriptions for TS_SEC_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_SEC_CNT

Write to the Seconds Counter.

0x0

R/W

Nanoseconds Counter Register

Address: 0x83, Reset: 0x00000000, Name: TS_NS_CNT

Use this register to write to the nanoseconds counter.

Table 87. Bit Descriptions for TS_NS_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_NS_CNT

Write to the Nanoseconds Counter. Note that this register must be programmed with a value that is divisible by

16 decimal. This is because the counters are driven by a 120 MHz clock and increment in steps of 16.

0x0

R/W

Timer Configuration Register

Address: 0x84, Reset: 0x00000000, Name: TS_CFG

Table 88. Bit Descriptions for TS_CFG

Bits

Bit Name

Description

Reset

Access

[31:5]

RESERVED

Reserved.

0x0

TS_CAPT_FREE_CNT

Capture the Free Running Counter. When this bit is 1 and FTSS is 0, time stamps are captured from

the 32-bit free running counter.

0x0

R/W

If this bit is 0 and FTSS is 0, 32-bit time stamps as defined in the OPEN Alliance MACPHY

specification are captured.

If FTSS is 1, 64- bit time stamps as defined in the OPEN Alliance MACPHY specification are

captured.

TS_TIMER_STOP

Stop Toggling the TS_TIMER Output. Write 1 to this bit to stop the TS_TIMER output toggling and

return it to its default value. Write to the TS_TIMER_START registers to start the TS_TIMER output

signal again.

0x0

This bit automatically clears to 0.

TS_TIMER_DEF

Default Value for the TS_TIMER Output. To change the default value of the TS_TIMER from 0, write

1 to this field before enabling the TS_TIMER (it is enabled when TS_TSTART is written). Note that

on writing 1 to this register, the TS_TIMER output immediately toggles from 0 to 1. Writing to this

field has no effect if the TS_TIMER is already enabled. If P1_LED_0 is used as the TS_TIMER

output, the default value is dependent on the P1_LED_0 polarity set by the LED0_POLARITY bit

field.

0x0

R/W

TS_CLR

Clear the 1588 Time Stamp Counters. Write to 1 to reset the time stamp counters to 0. This field

automatically clears to 0 after it is written to 1. Four counters are cleared, the accumulator, the

nanoseconds counter, the seconds counter, and the free running counter.

0x0

TS_EN

Enable the 1588 Time Stamp Counter. When this bit is 1, the time stamp counter is enabled and

time stamps are captured for all received frames. The counters are not cleared when TS_EN is 0.

Instead, the counters freeze. Therefore, it is recommended to write to use TS_CLR after disabling

the counters to get them to a known state before starting again.

0x0

R/W

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