ADIN2111CCPZ-R7 datasheet(11/129 Pages) AD

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Data Sheet

ADIN2111

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 129

Table 8. Pin Function Descriptions (Continued)

Pin No.

Mnemonic1

PU/PD2

Description

Configure the Device to Use 8-bit CRC (generic SPI mode) or Protection Mode (OPEN

Alliance Mode) on the SPI Host Interface (SPI_CFG0). Use this pin with SPI_CFG1. See

Table 22 for details. The default configuration for this pin is with protection/CRC enabled.

This pin is provided with an internal pull-up resistor.

SCLK

Clock Input. Data is clocked into the shift register on each falling edge.

Active Low Chip Select.

Reset

RESET

Hardware Reset, Active Low Input. Hold low for >10 μs to reset the device. This pin can be

left floating if a hardware reset is not required. See the Hardware Reset section.

Media Dependent Interface (MDI)

P2_TXN

N/A

Port 2 10BASE-T1L Transmit/Receive Negative Pin.

P2_TXP

N/A

Port 2 10BASE-T1L Transmit/Receive Positive Pin.

P1_TXN

N/A

Port 1 10BASE-T1L Transmit/Receive Negative Pin.

P1_TXP

N/A

Port 1 10BASE-T1L Transmit/Receive Positive Pin.

Configuration/Status/Test

TEST_3

Test Pin 3. No function currently assigned. Do not connect.

TEST_2

Test Pin 2. No function currently assigned. Do not connect.

P1_LED_0/ SPI_CFG1

General-Purpose, Programmable LED Indicator 0 for Port 1 (P1_LED_0). The LED can

be active high or active low. By default, P1_LED_0 is configured to turn on when a link is

established and blink when there is activity. The default LED function is Tx/Rx activity. The

default configuration is P1_LED_0 enabled. See the Status LEDs section.

Configure the device to Use OPEN Alliance SPI Mode or Analog Devices SPI Mode

(SPI_CFG1). A voltage high level on this pin enables SPI generic mode. A voltage low

level on this pin enables SPI OA mode. For OPEN Alliance SPI mode, use without LED,

connect an external pull-down of 4.7 kΩ or less. Use this pin with SPI_CFG0. See Table

22 for details. The default configuration is generic SPI. This pin is provided with an internal

pull-up resistor.

P1_LED_1/P1_TX2P4_EN

General-Purpose, Programmable LED Indicator 1 for Port 1 (P1_LED_1). The LED can

be active high or active low. The default condition is P1_LED_1 disabled. See the Status

LEDs section.

Port 1 Transmit Level Amplitude Hardware Configuration Pin Signal (P1_TX2P4_EN). Set

high for 1.0 V p-p transmit amplitude only. Set low to support both 1.0 V p-p and 2.4 V p-p

transmit amplitude. See Table 19. This pin is provided with an internal pull-down resistor.

TEST_1

Test Pin 1. This pin can be assigned to the TS_CAPT alternative function using the

DIGIO_TSCAPT_PINMUX bit in the Pin Mux Configuration 1 register. Do not connect if

unused.

TEST_0/P1_SWPD_EN

Test Pin 0 (TEST_0). No function currently assigned.

Disable Port 1 PHY Software Power-Down After Power-Up/Reset (P1_SWPD_EN). When

software power-down (SWPD) is enabled, a reset or power cycle puts the chip in active

mode and attempts to link up and switch forward all frames. The default configuration is

SWPD enabled. To disable SWPD, connect a 4.7 kΩ or less external pull-up resistor to

VDDIO. This pin is provided with an internal pull-down resistor.

P2_LED_0/P2_SWPD_EN

General-Purpose, Programmable LED Indicator 0 for Port 2 (P2_LED_0). The LED can

be active high or active low. By default, P2_LED_0 is configured to turn on when a link is

established and blink when there is activity. The default LED function is Tx/Rx activity. The

default configuration is P2_LED_0 enabled. See the Status LEDs section.

Disable Port 2 PHY Software Power-Down After Power-Up/Reset (P2_SWPD_EN). When

SWPD is enabled, a reset or power cycle puts the chip in active mode and attempts to link

up and switch forward all frames. The default configuration is SWPD disabled. To disable

SWPD, pull the pin high or leave the pin floating. This pin is provided with an internal

pull-up resistor.

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