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ADIN2111CCPZ-R7 Folha de dados(PDF) 7 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  129 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADIN2111CCPZ-R7 Folha de dados(HTML) 7 Page - Analog Devices

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Data Sheet
ADIN2111
TIMING CHARACTERISTICS
analog.com
Rev. A | 7 of 129
POWER-UP TIMING
Table 3. Power-Up Timing
Parameter
Description
Min
Typ
Max
Unit
tRAMP
Power supply ramp time
40
ms
t1
Minimum time interval to internal power good1
20
43
ms
t2
Hardware configuration latch time
6
8
14
μs
t3
Management interface (SPI) active
50
ms
1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required.
Figure 2. Power-Up Timing
SPI
Table 4.
Parameter1, 2
Description
Min
Typ
Max
Unit
t1
SCLK cycle time
40
ns
t2
SCLK high time
17
ns
t3
SCLK low time
17
ns
t4
CS falling edge to SCLK rising edge setup time
17
ns
t5
Last SCLK rising edge to CS rising edge
17
ns
t6
CS high time
40
ns
t7
Data setup time
5
ns
t8
Data hold time
5
ns
t9 3
SCLK falling edge to SDO valid
12
ns
t10 3
CS rising edge to SDO tristate
15
ns
t11 3
CS falling edge to SDO valid (for readback MSB only)
12
ns
1 Guaranteed by design and characterization. Not production tested.
2 All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDDIO) and timed from a voltage level of 1.2 V.



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