ADIN2111CCPZ-R7 datasheet(100/129 Pages) AD

100 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 100 of 129

Table 176. Bit Descriptions for B10L_PMA_CNTRL

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

R/W SC

B10L_TX_DIS_MODE_EN

10BASE-T1L Transmit Disable Mode. When this bit is set to 1, it disables output on the

transmit path. Otherwise, it enables output on the transmit path.

0x0

R/W

RESERVED

Reserved.

0x0

B10L_TX_LVL_HI

10BASE-T1L Transmit Voltage Amplitude Control. This configuration is only used

when autonegotiation is disabled. Otherwise, the configuration is decided by the

autonegotiation process. When this bit is set as 1, the device works in the 2.4 V p-p

operating mode. Otherwise, the device works in the 1.0 V p-p operating mode.

Pin dependent

R/W

RESERVED

Reserved.

0x0

R/W

B10L_EEE

10BASE-T1L EEE Enable.

0x0

R/W

[9:1]

RESERVED

Reserved.

0x0

B10L_LB_PMA_LOC_EN

10BASE-T1L PMA Loopback. When this bit is set to 1, the PMA accepts data on the

transmit path and returns it on the receive path. When this bit is set to 0, the PMA

works in normal mode.

0x0

R/W

10BASE-T1L PMA Status Register

Device Address: 0x01; Register Address: 0x08F7, Reset: 0x2800, Name: B10L_PMA_STAT

This address corresponds to the 10BASE-T1L PMA status register specified in Clause 45.2.1.186b of Standard 802.3cg

Table 177. Bit Descriptions for B10L_PMA_STAT

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

B10L_LB_PMA_LOC_ABLE

10BASE-T1L PMA Loopback Ability. This bit always reads as 1 because the

PMA has loopback ability.

0x1

B10L_TX_LVL_HI_ABLE

10BASE-T1L High Voltage Tx Ability. Indicates that the PHY supports 10BASE-

T1L high voltage (2.4 V p-p) transmit level operating mode.

Pin dependent

B10L_PMA_SFT_PD_ABLE

PMA Supports Power-Down. Indicates that the PMA supports software power-

down.

0x1

B10L_EEE_ABLE

10BASE-T1L EEE Ability. Indicates if the PHY supports 10BASE-T1L EEE.

0x0

[9:0]

RESERVED

Reserved.

0x0

10BASE-T1L Test Mode Control Register

Device Address: 0x01; Register Address: 0x08F8, Reset: 0x0000, Name: B10L_TEST_MODE_CNTRL

This address corresponds to the 10BASE-T1L PMA test mode control register specified in Clause 45.2.1.186c of Standard 802.3cg. The default

value of this register selects normal operation without management intervention as the initial state of the device.

Table 178. Bit Descriptions for B10L_TEST_MODE_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:13]

B10L_TX_TEST_MODE

10BASE-T1L Transmitter Test Mode.

0x0

R/W

000: normal operation.

001: Test Mode 1—transmitter output voltage and timing jitter test mode. When Test Mode 1 is

enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1).

010: Test Mode 2—transmitter output droop test mode. When Test Mode 2 is enabled, the PHY

transmits ten +1 symbols followed by ten −1 symbols.

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