ADIN2111CCPZ-R7 datasheet(76/129 Pages) AD

76 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 76 of 129

TS_CAPT Pin 1 Time Stamp Register

Address: 0x8A, Reset: 0x00000000, Name: TS_EXT_CAPT1

Time Stamp Captured on the Assertion of the TS_CAPT Pin.

Table 94. Bit Descriptions for TS_EXT_CAPT1

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_EXT_CAPTD, Bits[63:32]

Time Stamp Captured on the Assertion of TS_CAPT Pin.

0x0

TS_CAPT Free Running Counter Register

Address: 0x8B, Reset: 0x00000000, Name: TS_FREECNT_CAPT

Capture of the free running counter when TS_CAPT asserts.

Table 95. Bit Descriptions for TS_FREECNT_CAPT

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_CNT_CAPTD

Captured Free Running Counter. This 32-bit counter is captured on the assertion of TS_CAPT pin, as is

TS_EXT_CAPT.

0x0

P1 MAC Rx Frame Size Register

Address: 0x90, Reset: 0x00000000, Name: P1_RX_FSIZE

Table 96. Bit Descriptions for P1_RX_FSIZE

Bits

Bit Name

Description

Reset

Access

[31:11]

RESERVED

Reserved.

0x0

[10:0]

P1_RX_FRM_SIZE

Receive Frame Size. The size of the frame at the head of the Rx FIFO in bytes. The size includes the

appended header. When using the generic SPI protocol this register must be read before reading a

frame from a receive FIFO via P1_RX.

0x0

P1 MAC Receive Register

Address: 0x91, Reset: 0x00000000, Name: P1_RX

The receive FIFO is read via this register. It is possible to burst read data from the Rx FIFO over SPI.

Table 97. Bit Descriptions for P1_RX

Bits

Bit Name

Description

Reset

Access

[31:0]

P1_RDR

Receive Data Register. This field is only used with the generic SPI protocol. Reading this register returns the four

bytes at the top of the receive FIFO and pops these four bytes from the FIFO. The upper 8 bits contain the first

byte, the next 8 bits contain the second byte, and so on. When a complete frame is read out, no further data is

returned from the P1 Rx FIFOs until the P1_RX_FRM_SIZE register is read first. Only used with the generic SPI

protocol.

0x0

P1 Rx Frame Count Register

Address: 0xA0, Reset: 0x00000000, Name: P1_RX_FRM_CNT

Table 98. Bit Descriptions for P1_RX_FRM_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

P1_RX_FRM_CNT

Rx Frame Count. This counter increments for received good and bad frames.

0x0

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