ADIN2111CCPZ-R7 datasheet(61/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 61 of 129

Table 52. Bit Descriptions for STATUS0 (Continued)

Bits

Bit Name

Description

Reset

Access

LOFE

Loss of Frame Error. When set, this bit indicates that the MACPHY detected an early deassertion of CS prior to

the expected end of a data chunk or command control transaction. Note that this bit field also asserts if CDPE

asserts.

0x0

R/W1C

RXBOE

Receive Buffer Overflow Error. When set, this bit indicates that the receive buffer (from the network) overflowed

and the receive frame data was lost.

0x0

R/W1C

TXBUE

Host Tx FIFO Under Run Error. This error can only assert when cut through from the host is enabled. The host

software ensures this bit never asserts by writing frame data to the MAC at a rate greater than 10 Mbps. If an

under run error occurs, transmit of the current packet stops.

0x0

R/W1C

TXBOE

Host Tx FIFO Overflow. The host software ensures this bit never asserts by checking the space available in

the Tx FIFO before writing to the Tx FIFO. If using the OPEN Alliance SPI Data protocol, the space in the Tx

FIFO is indicated in the TXC field of the Rx footer. If using the generic SPI protocol, the TX_SPACE register

indicates the remaining space in the Tx FIFO. If the host Tx FIFO overflows, the frame being written is dumped

and software can chose to resend the entire frame. Writes to the FIFO commence at the next SOF. There is

always room for more than one frame in the host Tx FIFO as it is 4 kB (or greater) in size. Therefore, a frame

currently being transmitted is not interrupted by an overflow on the write side of the FIFO.

0x0

R/W1C

TXPE

Transmit Protocol Error. When set, this bit indicates that a Tx data chunk protocol error occurred. Data chunk

received with DV = 1 but without a prior SV = 1. Data chunk received with SV = 1 but with no EV = 1 (repeated

SV = 1 received). When using the generic SPI protocol, this bit indicates that the previous frame was not fully

written. A write of the TX_FSIZE register was detected, but the MAC still expects further writes to the Tx register

related to the previous frame size written to the TX_FSIZE register.

0x0

R/W1C

Status Register 1

Address: 0x09, Reset: 0x00000000, Name: STATUS1

Table 53. Bit Descriptions for STATUS1

Bits

Bit Name

Description

Reset

Access

[31:25]

RESERVED

Reserved.

0x0

R/W1C

P2_TXFCSE

CRC Mismatch on a Tx Frame on Port 2.

0x0

R/W1C

P2_RX_IFG_ERR

Rx MAC Interframe Gap Error. If the IFG is too short, the frame is dropped on receive. The threshold

used for measuring the IFG on receive can be set in the P2_RX_IFG register.

0x0

R/W1C

P2_TTSCAC

Transmit Time Stamp Capture Available C.

0x0

R/W1C

P2_TTSCAB

Transmit Time Stamp Capture Available B.

0x0

R/W1C

P2_TTSCAA

Transmit Time Stamp Capture Available A.

0x0

R/W1C

P2_PHYINT

PHY Interrupt for Port 2. Host software must read the MDIO Interrupt Status registers (PHY_SUB-

SYS_IRQ_STATUS or CRSM_IRQ_STATUS) on PORT2 PHY to determine the source of the interrupt.

0x0

P2_RX_RDY_HI

Port 2 Rx Ready High Priority. Indicates that there is a high priority frame available on Port 2. See

P1_RX_RDY_HI. This field does not drive the interrupt pin. This field is only used with the generic SPI

protocol.

0x0

P2_RX_RDY

Port 2 Rx FIFO Contains Data. In store and forward mode, this field indicates that there is one or

more frames in Port 2 Rx FIFO. In cut through mode, this field indicates that the receive threshold

(RX_THRESH) is reached or the EOF byte of a frame is received. If there are frames in both the Rx high

and low priority FIFOs, the frame from the high priority FIFO is read first by default. This default operation

can be changed using the RX_LOW_PRI_1ST field. This field is only used with the generic SPI protocol.

0x0

[16:13]

RESERVED

Reserved.

0x0

TX_ECC_ERR

ECC Error on Reading the Frame Size from a Tx FIFO. An uncorrectable ECC error was detected on a

read of the size field from the Tx FIFO. The FIFO is automatically cleared and the frame associated with

the ECC error and any other frames in the Tx FIFO is lost/dropped.

0x0

R/W1C

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