ADIN2111CCPZ-R7 datasheet(25/129 Pages) AD

25 / 129 page

Data Sheet

ADIN2111

BRINGING UP 10BASE-T1L LINKS

analog.com

Rev. A | 25 of 129

OVERVIEW

The Unmanaged PHY Operation section and Managed PHY Oper-

ation section provide some recommendations on how to bring a

link up between the ADIN2111 and a remote link partner. These

sections cover various configurations, and some may not be rele-

vant to the intended application. Refer to the Theory of Operation

section for more detailed explanations.

UNMANAGED PHY OPERATION

For an unmanaged PHY where there is no control of the ADIN2111

over the management interface, the hardware configuration pins

determine the operating mode for each PHY (see the Hardware

Configuration Pins section). In this context, the device is configured

to run in cut through mode (Port 1 to Port 2 forwarding)

The Disable Software Power-Down Mode After Reset section and

Set Transmit Amplitude Level section describe the steps required to

bring up a link in unmanaged applications.

Disable Software Power-Down Mode After

Reset

Software power-down mode after reset can be disabled for PHY 1

by asserting the P1_SWPD_EN (respectively P2_SWPD_EN) pin

signal high during power-up, hardware reset, or software reset, so

that PHY 1 does not enter software power-down mode when it exits

reset.

Software power-down mode after reset is disabled on PHY 2 by

default (due to the internal pull-up resistor).

See the Software Power-Down After Reset section for details on

how to configure the software power-down after reset function.

Set Transmit Amplitude Level

The P1_TX2P4_EN (respectively P2_TX2P4_EN) pin signal config-

ures the PHY 1 (respectively PHY 2) to advertise the support of

both 1.0 V p-p and 2.4 V p-p transmit level operation, or to only

advertise support of the 1.0 V p-p transmit level operation.

By default, PHY 1 and PHY 2 are configured to support 1.0 V p-p

and 2.4 V p-p transmit levels (due to the internal pull-down resistor).

Assert the relevant pin high or low to disable the support for the 2.4

V p-p transmit level on the relevant port.

See the Transmit Amplitude section for details on how to configure

the transmit amplitude level.

MANAGED PHY OPERATION

In a managed PHY application, a host controller such as a micro-

controller is used to configure the ADIN2111 operation in software

via the SPI interface.

Similar to the unmanaged PHY operation, the hardware configura-

tion pins can be used to set up the controlled ADIN2111 (see the

Unmanaged PHY Operation section for details). Alternatively, the

hardware configuration pins can directly be controlled by the host

(for example, GPIO) via an external pull-up or pull-down resistor or

both.

In managed applications, the software power-down after reset can

be enabled. The ADIN2111 stays in software power-down mode

until the software has configured the PHY to be active. When

active, the PHY can start autonegotiation and try to bring up a link.

Power-Up and Reset Complete

A typical way for software to verify that the device has completed

the power-up and reset sequence and is available for normal

operation is to read the management register that has the IEEE or-

ganizationally unique identifier (OUI), model, and revision numbers.

The value of this register is unique to each PHY vendor and is a

nonzero value. If the device has not completed the power-up, the

value does not read properly. In legacy BASE-T PHYs, this value

is at management interface Register Address 0x2 and Register

Address 0x3.

In the ADIN2111, the OUI, model number, and revision numbers

can be read from the PHY identification register (PHYID). If the

reset value of the register (0x283BCA1) can be read, the device

exited reset and is ready for configuration. These fields can also

be read at Device Address 0x1F Clause 45 only), Register Address

0x2, and Register Address 0x3 (Clause 22 and Clause 45).

The OUI Bits[3:18] are located in the Vendor Specific MMD 1

device identifier high register (MMD1_DEV_ID1).

The OUI Bits[19:24] (MMD1_DEV_ID2_OUI), the model number

Bits[6:0] (MMD1_MODEL_NUM), and the revision number Bits[6:0]

(MMD1_REV_NUM) are located in the Vendor Specific MMD 1

device identifier low register (MMD1_DEV_ID2).

Table 23. ADIN2111 Unique Identifier Values

Description

Bit Name

Value

Organizationally Unique Identifier,

Bits[3:18]

MMD1_DEV_ID1

0x283

Organizationally Unique Identifier,

Bits[19:24]

MMD1_DEV_ID2_OUI

0x2F

Model Number, Bits[6:0]

MMD1_MODEL_NUM

0x8

Revision Number, Bits[6:0]

MMD1_REV_NUM

0x1

When a valid read of the IEEE OUI is done, the system ready

bit (CRSM_SYS_RDY) in the system status register (CRSM_STAT)

can also be read to verify that the start-up sequence is complete

and the system is ready for normal operation.

The software power-down status bit (CRSM_SFT_PD_RDY) in the

system status register (CRSM_STAT) is accessible on each PHY

and can be read to check if the relevant PHY is in the software

power-down state. This bit is also controlled by the P1_SWPD_EN

ADIN2111CCPZ-R7 Folha de dados(PDF) 25 Page - Analog Devices

ADIN2111CCPZ-R7 Folha de dados(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL