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ADIN2111CCPZ-R7 Folha de dados(PDF) 72 Page - Analog Devices |
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ADIN2111CCPZ-R7 Folha de dados(HTML) 72 Page - Analog Devices |
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72 / 129 page ![]() Data Sheet ADIN2111 REGISTERS analog.com Rev. A | 72 of 129 Table 79. Bit Descriptions for CECC_ERRn Bits Bit Name Description Reset Access [31:10] RESERVED Reserved. 0x0 R [9:0] CECC_ERR_CNT Corrected ECC Error Count. The seven counters map to FIFOs is as follows: 0x0 R CECC_ERR0: low priority Rx FIFO for Port 1. CECC_ERR1: high priority Rx FIFO for Port 2. CECC_ERR2: low priority Rx FIFO for Port 2 (LES only). CECC_ERR3: high priority Rx FIFO for Port 2 (LES only). CECC_ERR4: Tx FIFO from the host. CECC_ERR5: Port 1 to Port 2 Tx FIFO (LES only). CECC_ERR6: Port 2 to Port 1 Tx FIFO (LES only). MAC Address Rule and DA Filter Upper 16 Bits Registers Address: 0x50 to 0x6E (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_UPRn Contains the upper 16 bits of a MAC address and the forwarding rules associated with the MAC address. When writing the ADDR_FILT_x* registers, two register locations must be written in order for a given table entry. For example to write table entry 0, the registers must be written in the following order: 1: ADDR_FILT_UPR0. 2: ADDR_FILT_LWR0. Table 80. Bit Descriptions for ADDR_FILT_UPRn Bits Bit Name Description Reset Access 31 APPLY2PORT2 Apply to Port 2. 0x0 R/W 0: do not apply to Port 2. Do not apply this table entry/rule to frames received on Port 2. 1: apply to Port 2. Apply this table entry/rule to frames received on Port 2. 30 APPLY2PORT1 Apply to Port 1. 0x0 R/W 0: do not apply to Port 1. Do not apply this table entry/rule to frames received on Port 1. 1: apply to Port 1. Apply this table entry/rule to frames received on Port 1. [29:20] RESERVED Reserved. 0x0 R 19 HOST_PRI Host Rx Port Priority. On the receive port to the host, there are two FIFOs, a low priority FIFIO and a high priority FIFO. This field determines which FIFO the frame is placed in. Note that by default memory resources are provided for a high priority FIFO. However if the memory assigned to the high priority FIFO is moved to another FIFO by writing to the FIFO_SIZE register, this field must not be set to 1. 0x0 R/W 0: low priority. 1: high priority. 18 RESERVED Reserved. 0x0 R 17 TO_OTHER_PORT Forward Frames Matching this MAC Address to the Other Port. 0x0 R/W 16 TO_HOST Forward Frames Matching This MAC Address to the Host. If APPLY2PORT1 or APPLY2PORT2 is set to 1 and TO_HOST is 1, the frames matching this DA from the corresponding port are forwarded to the host. If TO_HOST is 0 and TO_OTHER_PORT is 0, frames matching the DA for this entry are dropped. 0x0 R/W [15:0] MAC_ADDR, Bits[47:32] MAC Address. 0x0 R/W |
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