ADIN2111CCPZ-R7 datasheet(69/129 Pages) AD

69 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 69 of 129

Table 73. Bit Descriptions for SPI_INJ_ERR (Continued)

Bits

Bit Name

Description

Reset

Access

If set and using the OPEN Alliance SPI protocol for data transaction, the parity bit in the Rx footer is

inverted. Also, the time stamp parity bit in the in Rx footer is inverted.

If set and using the OPEN Alliance SPI protocol for protected control burst write transactions, starting

from the second word in a burst, the MSB of each echoed 32-bit word is inverted.

If set and using the OPEN Alliance SPI protocol for protected control read transactions, the MSB of

each 32-bit complement word is inverted.

If set and using the generic SPI protocol with protection enabled, the CRC8 returned on a register read

is inverted.

FIFO Sizes Register

Address: 0x3E, Reset: 0x02222222, Name: FIFO_SIZE

Before modifying the FIFO sizes, frame reception and transmission must be stopped and the FIFOs must be empty.

Configure ADDR_RULE to drop all frames and set Px_UNK2HOST and Px_UNK2Px to 0 to ensure all received frames are dropped.

Use LES_FIFO_CLR to reset the FIFOs. Then the FIFO sizes can be modified.

The total FIFO size must be less than or equal to 28 kB.

Table 74. Bit Descriptions for FIFO_SIZE

Bits

Bit Name

Description

Reset

Access

[31:28]

RESERVED

Reserved.

0x0

[27:24]

P2_TX_SIZE

Port 1 to Port 2 Transmit FIFO Size.

0x2

R/W

0000: 0 bytes.

0001: 2 kB.

0010: 4 kB.

0011: 6 kB.

0100: 8 kB.

0101: 10 kB.

0110: 12 kB.

0111: 14 kB.

1000: 16 kB.

[23:20]

P1_TX_SIZE

Port 2 to Port 1 Transmit FIFO Size.

0x2

R/W

0000: 0 Bytes.

0001: 2 kB.

0010: 4 kB.

0011: 6 kB.

0100: 8 kB.

0101: 10 kB.

0110: 12 kB.

0111: 14 kB.

1000: 16 kB.

[19:16]

P2_RX_HI_SIZE

Port 2 Rx High Priority FIFO Size.

0x2

R/W

0000: 0 kB.

0001: 2 kB.

0010: 4 kB.

0011: 6 kB.

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