ADIN2111CCPZ-R7 datasheet(73/129 Pages) AD

73 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 73 of 129

MAC Address DA Filter Lower 32 Bits Registers

Address: 0x51 to 0x6F (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_LWRn

Contains the lower 32 bits of a MAC address in the DA filter table.

A write to one of these registers must be preceded by a write to the corresponding ADDR_FILT_UPRn register.

Table 81. Bit Descriptions for ADDR_FILT_LWRn

Bits

Bit Name

Description

Reset

Access

[31:0]

MAC_ADDR, Bits[31:0]

MAC Address.

0x0

R/W

Upper 16 Bits of the MAC Address Mask Register

Address: 0x70 to 0x72 (Increments of 2), Reset: 0x0000FFFF, Name: ADDR_MSK_UPRn

The upper 16 bits of a MAC address mask in the DA mask table.

When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. They must be written in

order with the UPR register written first and the LWR register written last.

Table 82. Bit Descriptions for ADDR_MSK_UPRn

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

MAC_ADDR_MASK, Bits[47:32]

MAC Address Bit Mask for the Address Table.

0xFFFF

R/W

Lower 32 Bits of the MAC Address Mask Register

Address: 0x71 to 0x73 (Increments of 2), Reset: 0xFFFFFFFF, Name: ADDR_MSK_LWRn

The lower 32 bits of a MAC address mask in the DA mask table.

When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. They must be written in

order with the UPR register written first and the LWR register written last.

Table 83. Bit Descriptions for ADDR_MSK_LWRn

Bits

Bit Name

Description

Reset

Access

[31:0]

MAC_ADDR_MASK, Bits[31:0]

MAC Address Bit Mask for the Address Table.

0xFFFFFFFF

R/W

Time Stamp Accumulator Addend Register

Address: 0x80, Reset: 0x85555555, Name: TS_ADDEND

Table 84. Bit Descriptions for TS_ADDEND

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_ADDEND

Time Stamp Accumulator Addend.

0x85555555

R/W

Timer Update Compare Register

Address: 0x81, Reset: 0x3B9ACA00, Name: TS_1SEC_CMP

Table 85. Bit Descriptions for TS_1SEC_CMP

Bits

Bit Name

Description

Reset

Access

[31:0]

TS_1SEC_CMP

Time Stamp 1 Second Compare Value.

0x3B9ACA00

R/W

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