ADIN2111CCPZ-R7 datasheet(71/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 71 of 129

Table 74. Bit Descriptions for FIFO_SIZE (Continued)

Bits

Bit Name

Description

Reset

Access

1000: 16 kB.

Tx FIFO Frame Count Register

Address: 0x3F, Reset: 0x00000000, Name: TFC

For debug only. Number of frames in the transmit FIFO.

Table 75. Bit Descriptions for TFC

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x0

[8:0]

TFC

Number of Frames in the Tx FIFO.

0x0

Tx FIFO Valid Half Words Register

Address: 0x40, Reset: 0x00000000, Name: TXSIZE

Number of Valid Half Words (16 Bits) in the Host Tx FIFO.

Table 76. Bit Descriptions for TXSIZE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

TX_SIZE

Data in the Tx FIFO. Number of Half Words (16 Bits).

0x0

Host Tx Frames Dropped Due to FIFO Overflow Register

Address: 0x41, Reset: 0x00000000, Name: HTX_OVF_FRM_CNT

Table 77. Bit Descriptions for HTX_OVF_FRM_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

HTX_OVF_FRM_CNT

Counts Host Tx Frames Dropped Due to FIFO Overflow.

0x0

Address of a Detected ECC Error in Memory Register

Address: 0x42, Reset: 0x00000000, Name: MECC_ERR_ADDR

Table 78. Bit Descriptions for MECC_ERR_ADDR

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

MECC_ERR_ADDR

Address of an Uncorrectable ECC Error in Memory. This is the address of the first uncorrectable ECC

error detected. That is when either RX_ECC_ERR or TX_ECC_ERR assert. When RX_ECC_ERR

and TX_ECC_ERR are cleared, the register is opened to catch the address of the next ECC error.

SRAM is 16 bits wide and this address points to a location in SRAM.

0x0

Corrected ECC Error Counters Register

Address: 0x43 to 0x49 (Increments of 1), Reset: 0x00000000, Name: CECC_ERRn

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