ADIN2111CCPZ-R7 datasheet(48/129 Pages) AD

48 / 129 page

Data Sheet

ADIN2111

SWITCH SPI

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Rev. A | 48 of 129

space available as indicated by the transmit credit field (TXC) of

the previous data footer. In this condition, the ADIN2111 ignores

the transmit data chunk and sets the host transmit FIFO overflow

bit, and the frame data already in the buffer is dropped.

►

Transmit buffer under run. This error can only occur in cut

through mode. The SPI host must always send frame data to

the ADIN2111 faster than the network to avoid this error. When

this error occurs, the host transmit FIFO under run error bit is

set, and the ADIN2111 terminates the frame being transmitted

in a way that invalidates the frame. Additionally, the ADIN2111

ignores any additional frame data received from the SPI host

until it receives an end of frame indication (EV = 1).

►

Loss of framing error. This error occurs when the CS signal

is deasserted before the expected end of the data chunk or

control command. When this error occurs, any transmit frame in

progress is dropped, and any receive frame in progress of being

sent to the SPI host is terminated.

►

Receive buffer overflow. This error occurs when the SPI host

does not read frame data from the ADIN2111 fast enough. This

error can occur both in store and forward and cut through modes.

When this error occurs, the ADIN2111 terminates the frame

being received from the internal PHYs. In store and forward

mode, no portion of the frame is transferred to the SPI host. In

cut through mode, the ADIN2111 terminates the frame (EV = 1)

with frame drop set (FD = 1).

►

Control data protection error. The control data protection error

(CDPE) and the loss of frame error (LOFE) bits assert when

protection is enabled on the OPEN Alliance SPI and there is an

error on write data received from the host. The write does not

complete in this case. If possible, the software executes the write

again. If software does not know which configuration register

was written, the device may not be configured properly. In this

case, reset the ADIN2111 MAC by writing the RST_MAC_ONLY

keys to the software reset register.

SPI Access to the PHY Registers

The ADIN2111 provides indirect access to the two PHY manage-

ment registers via the internal SPI to MDIO bridge. The eight

MDIOACCn registers in the SPI register map are used to access

the PHY management registers. Each MDIOACCn register corre-

sponds to an MDIO transaction.

The MDC default speed is 2.5 MHz. Either a 2.5 MHz or 4.166 MHz

management data clock (MDC) frequency can be selected via the

MSPEED bits in the CONFIG2 register.

The MDIO master polls the TRDONE bits of the eight MDIOACCn

registers in round robin mode. When the MDIO master detects that

one of the TRDONE fields is 0, the MDIO master starts an MDIO

transaction. When the MDIO transaction completes, the TRDONE

bits are set to 1, and the master proceeds to check the TRDONE

bits of the next MDIOACCn register.

Each of the two PHYs has a fixed MDIO PHY address, as follows:

►

PHY 1 MDIO address: 0x1

►

PHY 2 MDIO address: 0x2

Note that MDIO_DEVAD is always written with the device ID of

the register being accessed. MDIO_PRTAD is set to the respective

PHY MDIO address, and MDIO_ST is written to 0x0 for Clause 45

access (this applies to all of the following Clause 45 examples).

MDIO PHY Address Determination

The ADIN2111 allows access to the two PHY registers via an SPI to

MDIO master bridge.

Each of the two PHYs has a fixed MDIO PHY address, as follows:

►

MDIO PHY Address 1: PHY 1

►

MDIO PHY Address 2: PHY 2

Clause 45 MDIO Operation Examples

Example write to PHY 1 Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Regis-

ter XYZ, MDIO_DEVAD = the device ID of Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x0(ADDR), MDIO_ST =

0x0, and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Optionally, poll MDIOACC0. TRDONE = 0x1 to determine that

the write address operation has completed.

4. Poll MDIOACC1. TRDONE = 0x1 to determine that the write

data operation completed.

Example read of PHY 1 Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Register

XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_OP = 0x3(RD) and TRDONE =

0x0.

3. Poll MDIOACC1. TRDONE = 0x1 to determine that the write

data operation completed. MDIOACC1. MDIO_DATA reflects

the content of MDIO Register XYZ.

Example write operation followed by a read to verify the write

operation:

1. Write MDIOACC0 with MDIO_DATA = the address of register

ABC and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Write MDIOACC2 MDIO_OP = 0x3(RD) and TRDONE = 0x0.

4. Poll MDIOACC2. TRDONE = 0x1 to verify that all operations

completed. MDIO_DATA reflects the content of register ABC.

Example of four consecutive writes. It is possible to write a com-

mand to all eight registers before checking any.

1. Write MDIOACC0 with MDIO_DATA = the address of Register

ABC and TRDONE = 0x0.

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