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ADIN2111CCPZ-R7 Folha de dados(PDF) 111 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  129 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
ADIN2111
REGISTERS
analog.com
Rev. A | 111 of 129
Table 207. Bit Descriptions for AN_STATUS_EXTRA (Continued)
Bits
Bit Name
Description
Reset
Access
[6:5]
AN_MS_CONFIG_RSLTN
Master/Slave Resolution Result. Determined as per master/slave configuration of IEEE
Standard 802.3. This is encoded as follows:
0x0
R
0: not run.
1: configuration fault.
2: success, PHY is configured as slave.
3: success, PHY is configured as master.
[4:1]
AN_HCD_TECH
Highest Common Denominator (HCD) PHY Technology. As selected by the priority
resolution function of IEEE Standard 802.3 Subclause 98.2.4.2. Consider all values that
are not shown to be reserved.
0x0
R
0: null (not run).
1: 10BASE-T1L.
0
AN_LINK_GOOD
Autonegotiation Complete Indication. This corresponds to the an_link_good state of IEEE
Standard 802.3 Subclause 98.5.1. This signal indicates completion of the autonegotiation
transmission, and that the enabled PHY technology is either bringing up its link or that it has
brought up its link. See also AN_COMPLETE, which is similar, but also indicates that the
PHY link is up.
0x0
R
PHY Instantaneous Status Register
Device Address: 0x07; Register Address: 0x8030, Reset: 0x0010, Name: AN_PHY_INST_STATUS
This register address provides access to instantaneous status indications. These values are not latched. The set of indications returned by this
register is a consistent set, that is, a set of values in effect at the time the register address is read.
Table 208. Bit Descriptions for AN_PHY_INST_STATUS
Bits
Bit Name
Description
Reset
Access
[15:5]
RESERVED
Reserved.
0x0
R
4
IS_AN_TX_EN
Autonegotiation Tx Enable Status. Autonegotiation transmit enable. This bit indicates that the autonegotiation
is active and controlling the transmitter, and arbitration has not yet reached the autonegotiation (AN) good
check state or the AN good state. That is, the link_control signals have not been set to enable.
0x1
R
3
IS_CFG_MST
Master Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the
PHY is operating as master (and not slave).
0x0
R
2
IS_CFG_SLV
Slave Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the
PHY is operating as slave (and not master).
0x0
R
1
IS_TX_LVL_HI
Tx Level High Status. Indicates that the PHY is operating with high transmit levels (2.4 V), and not low
transmit levels (1.0 V).
0x0
R
0
IS_TX_LVL_LO
Tx Level Low Status. Indicates that the PHY is operating with low transmit levels (1.0 V), and not low transmit
levels (2.4 V).
0x0
R
Vendor Specific MMD 1 Device Identifier High Register
Device Address: 0x1E; Register Address: 0x0002, Reset: 0x0283, Name: MMD1_DEV_ID1
This address corresponds to the Vendor Specific 1 MMD identifier register specified in Clause 45.2.11.1 of Standard 802.3 and allows 16 bits of
the organizationally unique identifier (OUI) to be observed.
Table 209. Bit Descriptions for MMD1_DEV_ID1
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD1_DEV_ID1
Organizationally Unique Identifier, Bits[3:18].
0x283
R



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