ADIN2111CCPZ-R7 datasheet(58/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 58 of 129

Table 50. Bit Descriptions for CONFIG0 (Continued)

Bits

Bit Name

Description

Reset

Access

[11:10]

TXCTHRESH

Transmit Credit Threshold. This field configures the number of transmit credits (TXC) of free buffer that must

be available for writing before INT asserts. Only applies to the OA SPI Protocol.

0x0

R/W

00: ≥ 1 credit.

01: ≥ 4 credits.

10: ≥ 8 credits.

11: ≥ 16 credits.

TXCTE

Transmit Cut Through Enable. This bit enables the cut through mode of the frame transfer through the

MACPHY device from the SPI host to the network. When cut through on Tx is enabled the host must ensure

that data is provided to the device at a rate of > 10 Mbps to ensure frame transmission does not under run.

0x0

R/W

RXCTE

Receive Cut Through Enable. This bit enables the cut through mode of the frame transfer through the

LES device from the network to the SPI host. Cut through must be enabled on device configuration

before receiving frames is enabled. That is, enable cut through before setting Px_FWD_UNK2HOST or

Px_FWD_UNK2Px or writing to the ADDR_FILT_x registers. RXCTE must be 0 when using the generic SPI

protocol.

0x0

R/W

FTSE

Frame Time Stamp Enable. This bit enables IEEE 1588 receive and transmit frame time stamps.

0x0

R/W

0: frame receive/transmit time stamps are disabled.

1: frame receive/transmit time stamps are enabled.

FTSS

Receive Frame Time Stamp Select. When supported by this MACPHY device and enabled by FTSE = 1, this

bit configures the size and format of the time stamps appended to received frames and captures on request

of transmit frames.

0x0

R/W

0: 32-bit time stamps.

1: 64-bit time stamps.

PROTE

Enable Control Data Read Write Protection. When set and using the OPEN Alliance SPI protocol, all control

data written to and read from the MACPHY is transferred with its complement for detection of bit errors. When

set and using the generic SPI protocol, a CRC8 must be provided on SDI, and read data on SDO provides a

CRC8. Note this bit cannot be written. Its value is set via sensing a pin on power-up.

0x0

SEQE

Enable Tx Data Chunk Sequence and Retry. When supported by this MACPHY device, this bit enables

MACPHY monitoring of the SEQ bit transmitted in the Tx data chunk header by the SPI host and TX data

chunk retries. Not supported. Only applies to the OA SPI Protocol.

0x0

R/W

0: Support for Tx data chunk sequence and retry is disabled. The MACPHY ignores the Tx header SEQ bit.

1: Support for Tx data chunk sequence and retry is enabled. The MACPHY monitors the SEQ bit in the Tx

header and allows the rewriting of Tx data chunks when the SEQ bit does not change.

RESERVED

Reserved.

0x0

[2:0]

CPS

Chunk Payload Selector (N). Chunk payload size is 2N. N = 3 minimum and 6 maximum. Default is 64 bytes.

This field must be set on device configuration before frame transmission from the host starts and before

enabling receiving frames into the Rx FIFOs. This field cannot be modified while transmitting a frame from

the host or while sending a received frame to the host. Once the configuration synchronization (SYNC) bit is

set, the chunk payload size must not be changed without a reset of the MACPHY. The minimum supported

chunk payload size for this MACPHY device is indicated in the CPSMIN field of the CAPABILITY register.

Only applies to the OA SPI protocol.

0x6

R/W

011: chunk size is 8 bytes.

100: chunk size is 16 bytes.

101: chunk size is 32 bytes.

110: chunk size is 64 bytes.

Configuration Register 2

Address: 0x06, Reset: 0x00000800, Name: CONFIG2

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