ADIN2111CCPZ-R7 datasheet(4/129 Pages) AD

4 / 129 page

Data Sheet

ADIN2111

SPECIFICATIONS

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Rev. A | 4 of 129

AVDD_H = AVDD_L = VDDIO = 3.3 V, DVDD_1P1 from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1), and all specifications

at −40°C to +105°C, unless otherwise noted.

Table 1. General Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUTS/OUTPUTS

Applies to the SPI pins, INT, RESET, and Px_LED_0 and

Px_LED_1 pins

VDDIO = 3.3 V

Input Low Voltage (VIL)

0.8

Input High Voltage (VIH)

2.0

Output Low Voltage (VOL)

0.4

Output low current (IOL) (minimum) = 2 mA

Output High Voltage (VOH)

2.4

Output high current (IOH) (minimum) = 2 mA

VDDIO = 2.5 V

VIL

0.7

VIH

1.7

VOL

0.4

IOL (minimum) = 2 mA

VOH

2.0

IOH (minimum) = 2 mA

VDDIO = 1.8 V

VIL

0.3 × VDDIO

VIH

0.7 × VDDIO

VOL

0.2 × VDDIO

IOL (minimum) = 2 mA

VOH

0.8 × VDDIO

IOH (minimum) = 2 mA

RESET Deglitch Time

0.3

0.5

µs

LED OUTPUT

Output Drive Current

VDDIO = 3.3 V

VDDIO = 2.5 V

VDDIO = 1.8 V

CLOCKS

External Crystal (XTAL)

Requirements for external crystal used on XTAL_I/CLK_IN

pin and XTAL_O pin

Crystal Frequency

MHz

Crystal Frequency Tolerance

−30

+30

ppm

Crystal Drive Level

<200

µW

Crystal Equivalent Series Resistance (ESR)

XTAL_I, XTAL_O Input Capacitance (CIN,EQ)

1.5

Equivalent parallel differential input capacitance looking into

XTAL_I/CLK_IN pin and XTAL_O pin

Crystal Load Capacitance (CL)1

Including PCB trace capacitance and XTAL_I, XTAL_O

CIN,EQ

Start-Up Time

Crystal oscillator only

Clock Input (CLK_IN)

Clock Input Frequency

MHz

Requirements for external clock applied to XTAL_I pin

Clock Input Voltage Range

0.8

2.5

V p-p

Clock Input Duty Cycle

Input clock duty cycle 50%

XTAL_I Input Impedance (ZIN,EQ)

Driving Point Resistance (RP)2

kΩ

RP||CP

Driving Point Capacitance (CP)2

Jitter Tolerance (RMS)

CLK25_REF Clock Output

CLK25_REF Frequency

MHz

VOH

1.05

Load = 10 pF

VOL

Load = 10 pF

CLK25_REF Duty Cycle

Load = 10 pF

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