ADIN2111CCPZ-R7 datasheet(24/129 Pages) AD

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Data Sheet

ADIN2111

HARDWARE CONFIGURATION PINS

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Rev. A | 24 of 129

When software power-down after reset is enabled on a port, the

associated ADIN2111 PHY enters software power-down after pow-

er-up, hardware reset, or software reset. Software power-down

provides a lower power mode where most of the ADIN2111 internal

modules are turned off.

The ADIN2111 PHYs can be configured to exit power-down by

setting the CRSM_SFT_PD bit to 0 using the SPI via the MDIO

bridge.

Following a power-up, hardware reset, or software reset, and if

autonegotiation is enabled and software power-down after reset is

disabled, the respective ADIN2111 PHY starts autonegotiation and

tries to bring up a link.

Table 18. Port 1/Port 2 Software Power-Down (Hardware Configuration)

Px_SWPD_EN

Software Power-Down Configuration

PHY in software power-down after reset

PHY not in software power-down after reset

Transmit Amplitude

The P1_TX2P4_EN (respectively P2_TX2P4_EN) hardware con-

figuration pin signal is shared with the P1_LED_1 (respectively

P2_LED_1) signal and is used to configure the default transmit

amplitude mode. The transmit amplitude mode is defined by the

pin status during power-up, hardware reset, or software reset as

defined in Table 19 and Table 20.

The Px_TX2P4_EN hardware configuration pin signals also con-

figure the default setting of the high voltage transmit ability bit

(B10L_TX_LVL_HI_ABLE) in the 10BASE-T1L PMA status register

(B10L_PMA_STAT) within the relevant PHY during power-up, hard-

ware reset, or software reset. The B10L_TX_LVL_HI_ABLE bit

reports whether the associated PHY is capable of operating in the

10BASE-T1L high transmit voltage mode, as described in Table 21.

If Px_TX2P4_EN is pulled low during power-up, hardware reset, or

software reset, the 2.4 V p-p transmit operating mode is enabled

and the value of B10L_TX_LVL_HI_ABLE is set to 1.

If Px_TX2P4_EN is pulled high during power-up, hardware reset, or

software reset, the 2.4 V p-p transmit operating mode is disabled,

and the value of B10L_TX_LVL_HI_ABLE is set to 0. In that case,

the associated register on the respective PHY cannot be changed

through the SPI. That is, 2.4 V p-p operation is not possible on the

respective PHY if it has been configured for the 1.0 V p-p level only

via the Px_TX2P4_EN pin.

The Px_TX2P4_EN pins have a weak internal pull-down resistor.

Therefore, by default, the ADIN2111 is configured to support both

1.0 V p-p and 2.4 V p-p voltage levels on Port 1 and Port 2.

Table 19. Port 1 Transmit Amplitude Selection (Hardware Configuration)

P1_TX2P4_EN

Transmit Amplitude Selection

1.0 V p-p and 2.4 V p-p

1.0 V p-p

Table 20. Port 2 Transmit Amplitude Selection (Hardware Configuration)

P2_TX2P4_EN

Transmit Amplitude Selection

1.0 V p-p and 2.4 V p-p

1.0 V p-p

Table 21. B10L_TX_LVL_HI_ABLE Settings

Bit Setting

Description

PHY does not support 10BASE-T1L high voltage (2.4 V p-p)

transmit level operating mode.

PHY supports 10BASE-T1L high voltage (2.4 V p-p) transmit

level operating mode.

SPI Protocol Configuration

The ADIN2111 allows the use of a generic SPI protocol with or

without the use of CRC, or the OPEN Alliance SPI protocol with or

without protection.

Table 22. SPI Protocol (Hardware Configuration)

SPI Protocol

SPI_CFG1

SPI_CFG0

OPEN Alliance with Protection

OPEN Alliance Without Protection

Generic SPI with 8-bit CRC

Generic SPI Without 8-bit CRC

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