ADIN2111CCPZ-R7 datasheet(10/129 Pages) AD

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Data Sheet

ADIN2111

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 10 of 129

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic1

PU/PD2

Description

Clock Interface

P2_CLK_IN

N/A

Single-Ended 25 MHz Reference Clock Dedicated to Port 2 PHY. This pin must be

connected to an external, single-ended 25 MHz reference clock, or to the CLK25_REF pin

(Pin 22), which provides a 25 MHz clock.

CLK25_REF

N/A

Analog Reference Clock Output. The 25 MHz reference clock from the crystal oscillator is

available on the CLK25_REF pin. The 25 MHz clock output is briefly disabled (logic low)

following a software reset (25 ms) or a hardware reset (70 ms). See the Reset Operations

section for more details.

XTAL_I/CLK_IN

N/A

Main Crystal/Single-Ended 25 MHz Reference Clock Input. This pin must be connected to

an external, single-ended 25 MHz reference clock. This clock source is also used by Port

1 PHY.

XTAL_O

N/A

Main Crystal Output. If using a single-ended reference clock on XTAL_I/CLK_IN, leave

XTAL_O open circuit. See the External 25 MHz Clock Input section.

SPI

INT

Interrupt Pin Output. Open-drain, active low output. A low on INT indicates an unmasked

management interrupt. This pin requires a 1.5 kΩ pull-up resistor to VDDIO.

SDI

Serial Data Input. Data is clocked in on the SDI pin on each rising edge.

SDO/SPI_CFG0

Serial Data Output (SDO). Data is clocked out on the SDO pin on each falling edge.

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