ADIN2111CCPZ-R7 datasheet(36/129 Pages) AD

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Data Sheet

ADIN2111

APPLICATIONS INFORMATION

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Rev. A | 36 of 129

Transistor Controlled LED

Figure 19 displays a typical configuration where the LED current

required is higher than what the Px_LED_0 and Px_LED_1 pins

can supply. The circuit operates using the active high LED mode.

An external transistor, such as an N channel metal-oxide semicon-

ductor field effect transistor (MOSFET), can be used. The transistor

must be selected so that the gate input capacitance is not sinking

current above the maximum rating of the Px_LED_x pin during

the actuation. Refer to the transistor technical specifications for

information. If required, the inrush current can be reduced by

placing a resistance between the transistor gate and the ADIN2111

pin, and/or adding a parallel capacitor between the GND and the

Px_LED_x pin. The additional resistor and capacitor values must be

defined based on the transistor selection.

Select the R0 and R1 resistors to control the LED current (refer to

the selected LED and transistor specifications of the manufacturer

for information).

External pull-down resistors (RPD0 and RPD1) with a value of 4.7 kΩ

are recommended. In Figure 19, VCC is the power supply used to

supply the LEDs.

Figure 19. Transistor Controlled LED Configuration

Autosense Polarity

In autosense mode, the polarity of the LED is automatically detect-

ed during power-up, hardware reset, or software reset. LED_0

(internal pull-up) and LED_1 (internal pull-down) have different

autosense behaviors due to their internal pull-up and pull-down

configurations. Use one of the configurations described in the

Active High LED Polarity, Active Low LED Polarity, and Transistor

Controlled LED sections so that the two LEDs can be controlled the

same way.

COMPONENT RECOMMENDATIONS

The ADIN2111 requires an external 25 MHz clock, which can be

sourced from an external crystal oscillator or an external single-

ended clock.

The signal voltage on the XTAL_I/CLK_IN pin (VCLK_IN) must be

a sine or filtered square wave signal with a peak-to-peak voltage

range from 0.8 V to 2.5 V. For the single-ended clock option, a

VCLK_IN with a 1.0 V p-p swing is recommended to achieve best

performance.

Various circuit configurations are proposed in the following sections.

A common circuit topology can be used across these options with a

change to the passive component values.

Note that during normal operation, a 25 MHz reference clock

generated from the external clock source input (a crystal or 25 MHz

external single-ended clock) is provided on the CLK25_REF output

pin. This pin can be used as a reference clock for other circuits,

such as another 10BASE-T1L device. CLK25_REF is disabled in

reset mode.

External Crystal Oscillator

The typical connection for an external crystal (XTAL) is shown in

Figure 20.

To ensure minimum current consumption and minimize stray ca-

pacitance, make connections between the crystal, capacitors, and

ground as close to the ADIN2111 as possible. Consult individual

crystal vendors for recommended load information and crystal per-

formance specifications.

The crystal load capacitance (CL) is defined by the crystal ven-

dor. CPCB1 and CPCB2 are the parasitic capacitance between the

XTAL_I/CLK_IN and XTAL_O and the ground plan beneath, respec-

tively. CX1 and CX2 are the two external load capacitors required for

the oscillator to operate.

Assuming the following:

►

CPCB1 ≈ CPCB2 ≈ CPCBx

►

CX1 ≈ CX2 ≈ CXx

Then, CXx = 2 × CL – CPCBx – 3 pF

Choose precision capacitors for CXx with low appreciable tempera-

ture coefficient to minimize frequency errors.

To ensure minimum current consumption and to minimize stray

capacitance, make the connections between the crystal, capacitors,

and ground as close to the ADIN2111 as possible.

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