ADIN2111CCPZ-R7 datasheet(66/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 66 of 129

Table 63. Bit Descriptions for MDIOACCn (Continued)

Bits

Bit Name

Description

Reset

Access

[15:0]

MDIO_DATA

Data/Address Value. For a write operation (Clause 45 or Clause 22), the SPI host must set this

to the 16-bit value to be written. For an address operation (Clause 45), the SPI host must set

this to the 16-bit register address value. For a read operation (Clause 45 or Clause 22), or for a

read-post-increment-address operation (Clause 45), the SPI host must set this value to 0. On completion

of the MDIO transaction (as indicated by TRDONE), the MACPHY sets this to the 16-bit value read.

0x0

R/W

MAC Tx Frame Size Register

Address: 0x30, Reset: 0x00000000, Name: TX_FSIZE

Table 64. Bit Descriptions for TX_FSIZE

Bits

Bit Name

Description

Reset

Access

[31:11]

RESERVED

Reserved.

0x0

[10:0]

TX_FRM_SIZE

Transmit Frame Size. This field indicates the size of the frame that is written to the transmit FIFO in bytes

when using the generic SPI protocol. The size must include the 2-byte frame header. This is used on the

SPI side of the Tx FIFO to determine when the full frame is written. When the full frame byte count is

reached, subsequent writes to MAC_TX register are ignored until the MAC_TXF_SIZE is written again. This

field is only used with the generic SPI protocol.

0x0

R/W

MAC Transmit Register

Address: 0x31, Reset: 0x00000000, Name: TX

The transmit FIFO is written via this register.

Table 65. Bit Descriptions for TX

Bits

Bit Name

Description

Reset

Access

[31:0]

TDR

Transmit Data Register. Writing to this register adds four bytes to the Host Tx FIFO. Note that the last word of a

frame can only contain less than four bytes of data. The hardware uses MAC_TXF_SIZE to determine if there is

one, two, three, or four bytes valid in the last SPI write of a frame. Only used with the generic SPI protocol.

0x0

Tx FIFO Space Register

Address: 0x32, Reset: 0x000007FF, Name: TX_SPACE

Table 66. Bit Descriptions for TX_SPACE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

TX_SPACE

Transmit FIFO Space Available in Half Words (16 Bits). This is used by the host software to determine if there is

space in the Tx FIFO for a frame. Note that the software can queue two frames for transmission and simply wait

for a TX_RDY interrupt, or it can fill the Tx FIFO with multiple frames and use TX_SPACE to determine if there

is space for the next frame. Note that an extra two words of space is needed per frame in the host TX FIFO to

store the frame size and header. For example, if TX_SPACE is 64, the maximum size frame that can be written

is (64 − 2) × 2 bytes = 124 bytes. Only used with the generic SPI protocol.

0x7FF

Transmit Threshold Register

Address: 0x34, Reset: 0x00000041, Name: TX_THRESH

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