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ADIN2111CCPZ-R7 Folha de dados(PDF) 85 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  129 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADIN2111CCPZ-R7 Folha de dados(HTML) 85 Page - Analog Devices

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Data Sheet
ADIN2111
REGISTERS
analog.com
Rev. A | 85 of 129
P2 MAC Loopback Enable Register
Address: 0xE3, Reset: 0x00000000, Name: P2_LOOP
Table 142. Bit Descriptions for P2_LOOP
Bits
Bit Name
Description
Reset
Access
[31:1]
RESERVED
Reserved.
0x0
R
0
P2_LOOPBACK_EN
MAC Loopback. Enable loopback on the MII to the PHY.
0x0
R/W
0: normal operation. Loopback disabled.
1: loopback enabled.
P2 CRC Check Enable on Receive Register
Address: 0xE4, Reset: 0x00000001, Name: P2_RX_CRC_EN
Table 143. Bit Descriptions for P2_RX_CRC_EN
Bits
Bit Name
Description
Reset
Access
[31:1]
RESERVED
Reserved.
0x0
R
0
P2_CRC_CHK_EN
CRC Check Enable on Receive.
0x1
R/W
P2 Receive Interframe Gap Register
Address: 0xE5, Reset: 0x0000000A, Name: P2_RX_IFG
Table 144. Bit Descriptions for P2_RX_IFG
Bits
Bit Name
Description
Reset
Access
[31:6]
RESERVED
Reserved.
0x0
R
[5:0]
P2_RX_IFG
Interframe Gap. The receive MAC checks that the IFG is greater than P2_RX_IFG × 8 bit times. If the received
IFG is too small, the MAC drops the received frame and asserts P2_RX_IFG_ERR. The maximum value
supported in this field is 63 decimal.
0xA
R/W
P2 Maximum Receive Frame Length Register
Address: 0xE6, Reset: 0x00000618, Name: P2_RX_MAX_LEN
Maximum receive frame length in bytes.
Table 145. Bit Descriptions for P2_RX_MAX_LEN
Bits
Bit Name
Description
Reset
Access
[31:16]
RESERVED
Reserved.
0x0
R
[15:0]
P2_MAX_FRM_LEN
Maximum Frame Length on Receive in Bytes.
0x618
R/W
P2 Minimum Receive Frame Length Register
Address: 0xE7, Reset: 0x00000040, Name: P2_RX_MIN_LEN
Minimum receive frame length in bytes.



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