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ADIN2111CCPZ-R7 Folha de dados(PDF) 88 Page - Analog Devices |
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ADIN2111CCPZ-R7 Folha de dados(HTML) 88 Page - Analog Devices |
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88 / 129 page  Data Sheet ADIN2111 REGISTERS analog.com Rev. A | 88 of 129 Table 155. Bit Descriptions for P2_TTSCBL Bits Bit Name Description Reset Access [31:0] P2_TTSCL_B Port 2 Transmit Time Stamp B, Bits[31:0]. 0x0 R Transmit Time Stamp Capture Register C (High) Address: 0xF4, Reset: 0x00000000, Name: P2_TTSCCH This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted. Table 156. Bit Descriptions for P2_TTSCCH Bits Bit Name Description Reset Access [31:0] P2_TTSCH_C Port 2 Transmit Time Stamp C, Bits[63:32]. 0x0 R Transmit Time Stamp Capture Register C (Low) Address: 0xF5, Reset: 0x00000000, Name: P2_TTSCCL This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted. Table 157. Bit Descriptions for P2_TTSCCL Bits Bit Name Description Reset Access [31:0] P2_TTSCL_C Port 2 Transmit Time Stamp C, Bits[31:0]. 0x0 R PHY CLAUSE 22 REGISTER DETAILS Register Summary: 10BASE-T1L Single Pair Ethernet PHY Core (ADIN2111) Table 158. ADIN2111 Register Summary Address Name Description Reset Access 0x0 MI_CONTROL MII Control Register. 0x1100 R/W 0x1 MI_STATUS MII Status Register. 0x1009 R 0x2 MI_PHY_ID1 PHY Identifier 1 Register. 0x0283 R 0x3 MI_PHY_ID2 PHY Identifier 2 Register. 0xBC01 R 0xD MMD_ACCESS_CNTRL MMD Access Control. 0x0000 R/W 0xE MMD_ACCESS MMD Access. 0x0000 R/W MII Control Register Address: 0x0, Reset: 0x1100, Name: MI_CONTROL This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3. Table 159. Bit Descriptions for MI_CONTROL Bits Bit Name Description Reset Access 15 MI_SFT_RST Software Reset. The software reset bit allows a software reset cycle to be initiated. Mirrors CRSM_SFT_RST. 0x0 R/W SC 14 MI_LOOPBACK Local Loopback (PCS). The loopback bit allows the PHY loopback mode to be engaged. Mirrors LB_PCS_EN. 0x0 R/W 13 MI_SPEED_SEL_LSB MII Speed Selection LSB. See MI_SPEED_SEL_MSB. 0x0 R |
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