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ADIN2111CCPZ-R7 Folha de dados(PDF) 15 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  129 Pages
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Data Sheet
ADIN2111
THEORY OF OPERATION
analog.com
Rev. A | 15 of 129
4 kB Port 2 PHY to host low priority receive FIFO
4 kB Port 1 to Port 2 transmit FIFO
4 kB Port 2 to Port 1 transmit FIFO
TRANSMIT AMPLITUDE CONFIGURATION
The ADIN2111 supports two transmit amplitude modes of operation,
as follows:
1.0 V p-p and 2.4 V p-p mode (high level)
1.0 V p-p only mode
The high level transmit operating mode allows the ADIN2111 to
support both voltage levels. The operating level can then be au-
tomatically configured during autonegotiation (if enabled) based
on the link partner capabilities. Note that in high level transmit
operating mode, AVDD_H must be supplied with 2.4 V or higher for
the device to work properly.
The mode of operation is configured through the P1_TX2P4_EN
(Port 1) and P2_TX2P4_EN (Port 2) hardware configuration pin
signals (see the Transmit Amplitude section). The ADIN2111 also
configures the default value for the transmit level register bits used
for the autonegotiation process based on the level configured on
those two pins (see the Transmit Amplitude Advertisement section).
The ADIN2111 is configured in high level transmit operating mode
by default on Port 1 (respectively Port 2) if the P1_TX2P4_EN
(respectively P2_TX2P4_EN) pin is left floating (internal pull-down
resistor).
MASTER/SLAVE CONFIGURATION
The 10BASE-T1L standard uses a master/slave clock scheme. This
scheme is commonly used in full duplex transceiver standards with
echo cancellation.
On a 10BASE-T1L link, one PHY is designated as the master, and
the other PHY as the slave. Autonegotiation is used to determine
which PHY is the master and which is the slave. Master and slave
assignment does not generally matter.
Software Configuration
The master and slave configuration bit (CFG_MST, accessible via
the MDIO bridge for each PHY) is used to configure the respective
PHY role. This bit is only used when autonegotiation is disabled.
Otherwise, this bit is set or reset during the autonegotiation process
(see the Autonegotiation section).
Table 9. CFG_MST Settings
Bit Setting
Description
0
Prefer slave
1
Prefer master
Table 10. Port 1 and Port 2 Master/Slave Default Configuration
Port
Master/Slave Configuration
Table 10. Port 1 and Port 2 Master/Slave Default Configuration (Continued)
Port
Master/Slave Configuration
1
Prefer master
2
Prefer slave
AUTONEGOTIATION
The ADIN2111 uses the autonegotiation capability in accordance
with IEEE 802.3 Clause 98, providing a mechanism for exchanging
information between the local device and link partners to agree to
a common mode of operation. Single twisted pair autonegotiation
is performed using differential Manchester encoding (DME) pages
exchanged between the local device and its link partner. At a high
level, autonegotiation provides the following functions:
Transmit
Receive
Half duplex
Arbitration
During the autonegotiation process, the local device advertises its
own capabilities and compares them to those received from the link
partner. The arbitration mechanism defines the operating modes
elected so that the transmit amplitude mode and master/slave
selection are configured for the linked devices.
If the link is dropped, the autonegotiation process restarts automat-
ically. An autonegotiation restart can also be requested by writing
to the autonegotiation restart bit (AN_RESTART) in the BASE-T1
autonegotiation control register (AN_CONTROL) of the respective
PHY.
The autonegotiation process can take time to complete, depending
on the number of pages exchanged, but is always the fastest way
to bring up a link. Clause 98 of the IEEE 802.3 standard details the
sequence timers and DME pages timing related to autonegotiation.
Autonegotiation is enabled by default for both ports of the
ADIN2111, and it is strongly recommended to always keep it en-
abled.
Transmit Amplitude Advertisement
High Voltage Transmit Ability Advertisement
The B10L_TX_LVL_HI_ABLE bit can be used on each PHY to
configure the default values for the autonegotiation advertisement
parameters. This bit is read only and configures Port 1 PHY
(respectively Port 2 PHY) ability advertisement based on the
P1_TX2P4_EN (respectively P2_TX2P4_EN) hardware configura-
tion pin signal, as described in the Transmit Amplitude section. The
transmit amplitude advertisement parameters are defined with the
following bits on each of the ADIN2111 PHYs:
AN_ADV_B10L_TX_LVL_HI_ABL: advertisement of the
10BASE-T1L high level transmit operating mode ability bit



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