ADIN2111CCPZ-R7 datasheet(60/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 60 of 129

Table 51. Bit Descriptions for CONFIG2 (Continued)

Bits

Bit Name

Description

Reset

Access

1: clear statistics counters on reading. If a counter reaches its maximum value, the counter

holds at its maximum until read. When using the generic SPI protocol, the status counters must

be burst read in one SPI transaction to ensure all counters are cleared correctly in sequence.

If a single SPI register/counter is read, it clears and the next counter (address location) also

clears when using the generic SPI protocol.

CRC_APPEND

Enable CRC Append in the MAC Tx Path. Enables (1) or disables (0) CRC appendage by

the MAC. If this field is set to 0, the MAC assumes that the host is providing a frame with a

valid CRC header at the end. It is recommended that the host always appends a CRC32 with

the frame as this provides errors detection over the SPI for transmitted frames. The CRC32

is checked as the frame is transmitted. If an error is detected, TXFCSE asserts. Similarly on

receive, the CRC32 is forwarded with the frame to the host where the host verifies it is correct.

0x0

R/W

P1_RCV_IFG_ERR_FRM

Admit Frames with IFG Errors on Port 1. If enabled, the MAC admits frames with IFG errors on

Port 1. Enables reception of frames that violate the minimum IFG requirement on Port 1.

0x0

R/W

RESERVED

Reserved.

0x0

R/W

P1_FWD_UNK2HOST

Forward Frames Not Matching Any MAC Address to the Host. Determines the default rule for

forwarding unknown frames. Frames with an unknown destination address are placed in the

low priority FIFO.

0x0

R/W

[1:0]

MSPEED

SPI to MDIO Bridge MDC Clock Speed.

0x0

R/W

00: 2.5 MHz.

01: 4.166 MHz.

Status Register 0

Address: 0x08, Reset: 0x00000040, Name: STATUS0

Table 52. Bit Descriptions for STATUS0

Bits

Bit Name

Description

Reset

Access

[31:13]

RESERVED

Reserved.

0x0

CDPE

Control Data Protection Error. When control data read/write protection is enabled, this bit indicates that the

MACPHY detected an error in protected control write data received from the host. When not implemented, this

bit is reserved with a read-only value of zero. This field is only used with the OPEN Alliance SPI protocol.

0x0

R/W1C

TXFCSE

Transmit Frame Check Sequence Error. This bit indicates that a frame was received over SPI from the host with

an invalid FCS appended. The frame is still forwarded from the device as the FCS is checked as the frame is

being transmitted.

0x0

R/W1C

TTSCAC

Transmit Time Stamp Capture Available C.

0x0

R/W1C

TTSCAB

Transmit Time Stamp Capture Available B.

0x0

R/W1C

TTSCAA

Transmit Time Stamp Capture Available A.

0x0

R/W1C

PHYINT

PHY Interrupt for Port 1. Host software must read the MDIO Interrupt Status registers (PHY_SUB-

SYS_IRQ_STATUS or CRSM_IRQ_STATUS) to determine the source of the interrupt. When exiting power-on

reset or pin reset this bit is asserted, but this field is masked from asserting an interrupt by default.

0x0

RESETC

Reset Complete. This bit is set when the MACPHY reset is complete and ready for configuration. When it is set,

it generates a nonmaskable interrupt assertion on INT to alert the SPI host. Additionally, setting the RESETC bit

also sets EXST = 1 in the first Rx footer, or until this bit is cleared by action of the SPI host writing a 1.

0x1

R/W1C

HDRE

Header Error. When set, this bit indicates that the MACPHY detected an invalid header received from the SPI

host. The invalid header is due to a parity check error. This field is only used with the OPEN Alliance SPI

protocol.

0x0

R/W1C

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