ADIN2111CCPZ-R7 datasheet(32/129 Pages) AD

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Data Sheet

ADIN2111

ON-CHIP DIAGNOSTICS

analog.com

Rev. A | 32 of 129

TEST MODES

The ADIN2111 provides several test modes for each PHY as descri-

bed in Subclause 146.5.2 from the IEEE 802.3cg-2019 standard

that allows testing of the transmitter waveform, distortion, jitter, and

droop. These test modes change only the data symbols provided

to the transmitter circuitry and do not alter the electrical and jitter

characteristics of the transmitter and receiver from the normal

operation.

Additionally, the ADIN2111 supports the transmit disable mode as

described in Subclause 45.2.1.186a.2.

Table 24. ADIN2111 Test Modes Summary

Test Mode

Description

PMA Test Modes

(Subclause 146.5.2)

Test Mode 1

Transmitter output voltage and timing jitter test mode.

When this mode is selected, the ADIN2111 repeatedly

transmits the data symbol sequence (+1, –1).

Test Mode 2

Transmitter output droop test mode. In this mode, the

ADIN2111 transmits ten +1 symbols followed by ten

−1 symbols. This sequence is repeated indefinitely.

Test Mode 3

Normal operation in idle mode test mode. In this

mode, the ADIN2111 transmits as in a nontest opera-

tion and in the master data mode with the data set to

normal interframe idle signals.

Transmit Disable Mode

(Subclause 45.2.1.186a.2)

Both transmit and receive paths act like in normal

operation mode, but only transmit 0 symbols. This

mode can be used to measure the MDI return loss

specified in Subclause 146.8.3.

Enable the PMA Test Mode 1 to Test Mode 3

Each of the ADIN2111 PHYs can be configured in one of the

PMA test modes (Test Mode 1 to Test Mode 3) using the following

procedure:

1. Enter software power-down mode by writing a 1 to the

CRSM_SFT_PD bit in the software power-down control register

(CRSM_SFT_PD_CNTRL).

2. Check that the ADIN2111 has entered software power-down

mode by reading the CRSM_SFT_PD_RDY bit in the system

status register (CRSM_STAT).

3. Disable autonegotiation by writing a 0 to the AN_EN bit in the

BASE-T1 autonegotiation control register (AN_CONTROL).

4. Set autonegotiation forced mode by writing a 1 to the

AN_FRC_MODE_EN bit in the autonegotiation force mode ena-

ble register (AN_FRC_MODE_EN).

5. Select the desired test mode by writing the appropriate value to

the B10L_TX_TEST_MODE bits in the 10BASE-T1L test mode

control register (B10L_TEST_MODE_CNTRL).

6. Exit software power-down mode by writing 0 to the

CRSM_SFT_PD bit in the software power-down control register

(CRSM_SFT_PD_CNTRL).

Table 25. PMA Test Modes Configuration

PMA Test Mode

B10L_TX_TEST_MODE, Bits[15:13] (Binary)

Test Mode 1

001

Test Mode 2

010

Test Mode 3

011

Enable Transmit Disable Mode

Each of the ADIN2111 PHYs can be configured in transmit disable

mode using the following procedure:

1. Enter software power-down mode by writing a 1 to the

CRSM_SFT_PD bit in the software power-down control register

(CRSM_SFT_PD_CNTRL).

2. Check that the ADIN2111 has entered the software power-down

mode by reading the CRSM_SFT_PD_RDY bit in the system

status register (CRSM_STAT).

3. Disable autonegotiation by writing a 0 to the AN_EN bit in the

BASE-T1 autonegotiation control register (AN_CONTROL).

4. Set autonegotiation forced mode by writing a 1 to the

AN_FRC_MODE_EN bit in the autonegotiation force mode ena-

ble register (AN_FRC_MODE_EN).

5. Set the transmit disable mode by writing a 1 to the

B10L_TX_DIS_MODE_EN bit in the 10BASE-T1L PMA control

6. Exit software power-down mode by writing 0 to the

CRSM_SFT_PD bit in the software power-down control register

(CRSM_SFT_PD_CNTRL).

TIME DOMAIN REFLECTOMETRY (TDR)

Given that the 10BASE-T1L compliant PHY enables communication

over long cables, debugging a faulty cable can become costly and

difficult without the right tools. To help with this, Analog Devices

10BASE-T1L products provide a TDR engine that enables cable

fault detection, distance to fault, and cable length estimation.

The diagnostics solution is the combination of a highly accurate

on-chip TDR engine and a set of algorithms that run on a host

microcontroller, allowing maximum flexibility for a wide variety of

cables and more advanced cable diagnostic capabilities.

Figure 12. ADIN2111 TDR Engine

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