ADIN2111CCPZ-R7 datasheet(67/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 67 of 129

Table 67. Bit Descriptions for TX_THRESH

Bits

Bit Name

Description

Reset

Access

[31:12]

RESERVED

Reserved.

0x0

[11:6]

P2P_TX_THRESH

Port to Port Transmit Start Threshold in Cut Through. If port to port cut through

(PORT_CUT_THRU_EN) is enabled, this field determines the threshold in half words (16 bits)

at which frame transmission starts when the frames are forwarded from one port to the other. The

range of valid values for this field is 1 to 26 half words.

0x1

R/W

[5:0]

HOST_TX_THRESH

Host Transmit Start Threshold in Cut Through. When cut through on Tx is enabled

(TX_CUT_THRU_EN = 1), this field is used to set the threshold in half words (16 bits) at which

frame transmission starts for frames coming from the host. The range of valid values for this field is

1 to 26 half words.

0x1

R/W

LES Tx Priority Register

Address: 0x35, Reset: 0x00000000, Name: TX_PRI

Table 68. Bit Descriptions for TX_PRI

Bits

Bit Name

Description

Reset

Access

[31:3]

RESERVED

Reserved.

0x0

[2:0]

TX_HOST_PRI

Host Transmit Priority. When frames are queued to egress a port from both the host and the other port at the

same time, this field determines the ratio of access to the port. For example, if there is a stream of 128-byte

frames from Port 1 to Port 2, and the host is transmitting a stream of 128-byte frames on Port 2, and this field

is set to H50_P50, 50% of the frames transmitted are from the host.

0x0

R/W

The ratio is based on comparing the recent number of bytes transmitted from the host and the other port. 3

options are available: H50_P50, H100_P0, or H0_P100. Values outside of those listed below are reserved.

000: 50/50 host/port.

101: 100/0 host/port. The host is always guaranteed access to wire.

110: 0/100 host/port. Port to port traffic always gets priority.

MAC FIFO Clear Register

Address: 0x36, Reset: 0x00000000, Name: FIFO_CLR

Table 69. Bit Descriptions for FIFO_CLR

Bits

Bit Name

Description

Reset

Access

[31:4]

RESERVED

Reserved.

0x0

LES_P2P_FIFOS_CLR

Clear the Port to Port FIFOs on LES. If a frame is being transmitted from a Tx FIFO, transmission

stops and a bad CRC is appended to the frame. Writes to Rx FIFOs resume at the start of the next

received frame.

0x0

LES_FIFOS_CLR

Clear All FIFOs. If a frame is being transmitted from a Tx FIFO, transmission stops and a bad CRC

is appended to the frame. Writes to Rx FIFOs resume at the start of the next received frame.

0x0

RESERVED

Reserved.

0x0

MAC_RXF_CLR

Clear the Receive FIFOs. Writes to the Rx FIFOs resume at the start of the next frame.

0x0

Scratch Registers

Address: 0x37 to 0x3A (Increments of 1), Reset: 0x00000000, Name: SCRATCHn

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