ADIN2111CCPZ-R7 datasheet(105/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Table 192. Bit Descriptions for AN_ADV_ABILITY_L (Continued)

Bits

Bit Name

Description

Reset

Access

the master/slave configuration is a forced mode. (The configuration in AN_ADV_MST is

a forced configuration.) See IEEE Standard 802.3 Subclause 98.2.1.2.5 for more details.

[11:10]

AN_ADV_PAUSE

Pause Ability. This bit field advertises support for asymmetric and symmetric pause

functions on full duplex links. See IEEE Standard 802.3 Subclause 98.2.1.2.6 for more

details.

0x0

R/W

[9:5]

RESERVED

Reserved.

0x0

[4:0]

AN_ADV_SELECTOR

Selector. The value of this bit field is fixed at 00001, which is the IEEE 802.3 selector

value. See IEEE Standard 802.3 Subclause 98.2.1.2.1.

0x1

BASE-T1 Autonegotiation Advertisement Register, Bits[31:16]

Device Address: 0x07; Register Address: 0x0203, Reset: 0x4000, Name: AN_ADV_ABILITY_M

This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits [31:16], specified in Clause 45.2.7.21 of Standard 802.3.

Table 193. Bit Descriptions for AN_ADV_ABILITY_M

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

AN_ADV_B10L

10BASE-T1L Ability. This bit indicates that the device is compatible with 10BASE-T1L.

0x1

R/W

[13:5]

RESERVED

Reserved.

0x0

AN_ADV_MST

Master/slave Configuration. This bit advertises the master/slave configuration, as follows: 0: slave,

1: master. See also the AN_ADV_FORCE_MS bit, which determines whether this bit expresses

a preference or a forced value. See IEEE Standard 802.3 Subclause 98.2.1.2.3 (master/slave

configuration is Bit 4 of the transmitted nonce field).

Pin Dependent

R/W

[3:0]

RESERVED

Reserved.

0x0

BASE-T1 Autonegotiation Advertisement Register, Bits[47:32]

Device Address: 0x07; Register Address: 0x0204, Reset: 0x0000, Name: AN_ADV_ABILITY_H

This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[47:32], specified in Clause 45.2.7.21 of Standard 802.3.

Table 194. Bit Descriptions for AN_ADV_ABILITY_H

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

AN_ADV_B10L_TX_LVL_HI_ABL

10BASE-T1L High Level Transmit Operating Mode Ability. This

bit advertises that the PHY is capable of transmitting in the

high level (2.4 V p-p) transmit operating mode. This bit is

used with AN_ADV_B10L_TX_LVL_HI_REQ to configure the 10BASE-

T1L transmission level (2.4 V p-p or 1.0 V p-p). See the

AN_ADV_B10L_TX_LVL_HI_REQ bit for more details.

Pin dependent

R/W

AN_ADV_B10L_TX_LVL_HI_REQ

10BASE-T1L High Level Transmit Operating Mode Request. This

bit advertises that the PHY is requesting that high level (2.4 V

p-p) transmit operating mode be used. The transmit level is re-

solved as follows: If either PHY is not capable of high level trans-

mission (and has AN_ADV_B10L_TX_LVL_HI_ABL = 0), both PHYs

must use the low voltage (1.0 V p-p) transmit operating mode.

Otherwise, if either PHY requests high level transmission (and has

AN_ADV_B10L_TX_LVL_HI_REQ = 1), both PHYs must use the high volt-

Pin dependent

R/W

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