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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADIN2111CCPZ-R7 Folha de dados(PDF) 113 Page - Analog Devices |
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ADIN2111CCPZ-R7 Folha de dados(HTML) 113 Page - Analog Devices |
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113 / 129 page  Data Sheet ADIN2111 REGISTERS analog.com Rev. A | 113 of 129 This address can be used to check which interrupt requests have been triggered since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of CRSM_IRQ_STATUS go high even when the associated interrupts are not enabled. A reserved interrupt being triggered indicates a fatal error in the system. Table 214. Bit Descriptions for CRSM_IRQ_STATUS Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_LH Software Requested Interrupt Event. 0x0 R LH [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_LH Hardware Reset Interrupt. 0x1 R LH [11:0] RESERVED Reserved. 0x0 R LH System Interrupt Mask Register Device Address: 0x1E; Register Address: 0x0020, Reset: 0x1BFE, Name: CRSM_IRQ_MASK Controls whether or not the interrupt signal is asserted in response to various events. Table 215. Bit Descriptions for CRSM_IRQ_MASK Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_REQ Software Interrupt Request. Software can set this bit to generate an interrupt for system level testing. This bit always reads as 0 because it is self clearing. 0x0 R/W SC [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_EN Enable Hardware Reset Interrupt. Note that writing a 0 to this bit does not mask the interrupt because this bit is initialized when a hardware reset occurs. 0x1 R/W [11:0] RESERVED Reserved. 0xBFE R/W Software Reset Register Device Address: 0x1E; Register Address: 0x8810, Reset: 0x0000, Name: CRSM_SFT_RST Table 216. Bit Descriptions for CRSM_SFT_RST Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_SFT_RST Software Reset Register. The software reset bit allows the chip to be reset. When this bit is set, the chip fully initializes, almost equivalent to a hardware reset. 0x0 R/W SC Software Power-Down Control Register Device Address: 0x1E; Register Address: 0x8812, Reset: 0x0000, Name: CRSM_SFT_PD_CNTRL Table 217. Bit Descriptions for CRSM_SFT_PD_CNTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 CRSM_SFT_PD Software Power-down. The software power-down register puts the chip in a lower power mode. In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still possible. The default value for this register is configurable via the Px_SWPD_EN pin. This allows the chip to be held in power-down mode until an appropriate software initialization is performed. Pin Dependent R/W PHY Subsystem Reset Register Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST |
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