ADIN2111CCPZ-R7 datasheet(127/129 Pages) AD

127 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 127 of 129

Frame Generator Done Register

Device Address: 0x1F; Register Address: 0x8029, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H

and FG_NFRM_L registers.

Table 259. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_DONE

Frame Generator Done. This bit reads as 1 to indicate that the generation of frames has completed. When set,

this bit goes high and it latches high until it is unlatched by reading.

0x0

R LH

MAC Interface Loopbacks Configuration Register

Device Address: 0x1F; Register Address: 0x8055, Reset: 0x000A, Name: MAC_IF_LOOPBACK

MAC interface loopbacks configuration.

Table 260. Bit Descriptions for MAC_IF_LOOPBACK

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

MAC_IF_REM_LB_RX_SUP_EN

Suppress RX Enable. Suppress receiver to the MAC when MAC_IF_REM_LB_EN is

set.

0x1

R/W

MAC_IF_REM_LB_EN

MAC Interface Remote Loopback Enable. Receive data is looped back to the

transmitter.

0x0

R/W

MAC_IF_LB_TX_SUP_EN

Suppress Transmission Enable. Suppress transmission to the PHY when

MAC_IF_LB_EN is set.

0x1

R/W

MAC_IF_LB_EN

MAC Interface Loopback Enable. Transmit data is looped back to the receiver.

0x0

R/W

MAC Start Of Packet (SOP) Generation Control Register

Device Address: 0x1F; Register Address: 0x805A, Reset: 0x001B, Name: MAC_IF_SOP_CNTRL

Table 261. Bit Descriptions for MAC_IF_SOP_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

MAC_IF_TX_SOP_LEN_CHK_EN

Enable Tx SOP Preamble Length Check.

0x0

R/W

MAC_IF_TX_SOP_SFD_EN

Enable Tx SOP Signal Indication on SFD.

0x1

R/W

MAC_IF_TX_SOP_DET_EN

Enable the Generation of the Tx SOP Indication Signal.

0x1

R/W

MAC_IF_RX_SOP_LEN_CHK_EN

Enable RX SOP Preamble Length Check. If this bit is set and no SFD is received,

the RX SOP signal indication is set after eight bytes. Otherwise, the RX SOP is not

set if no SFD is received in the first eight bytes.

0x0

R/W

MAC_IF_RX_SOP_SFD_EN

Enable RX SOP Signal Indication on SFD Reception. If both

MAC_IF_RX_SOP_DET_EN and MAC_IF_RX_SOP_SFD_EN are set, the RX SOP

signal is set when the SFD is received. Otherwise, the RX SOP is set when RX_DV

is set. The RX SOP signal remains set until the end of the frame.

0x1

R/W

MAC_IF_RX_SOP_DET_EN

Enable the Generation of the Rx SOP Indication Signal.

0x1

R/W

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