ADIN2111CCPZ-R7 datasheet(120/129 Pages) AD

120 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 120 of 129

Vendor Specific MMD 2 Device Identifier Low Register

Device Address: 0x1F; Register Address: 0x0003, Reset: 0xBC01, Name: MMD2_DEV_ID2

Table 231. Bit Descriptions for MMD2_DEV_ID2

Bits

Bit Name

Description

Reset

Access

[15:10]

MMD2_DEV_ID2_OUI

OUI Bits.

0x2F

[9:4]

MMD2_MODEL_NUM

Model Number.

0xA

[3:0]

MMD2_REV_NUM

Revision Number.

0x1

Vendor Specific 2 MMD Devices in Package Register

Device Address: 0x1F; Register Address: 0x0005, Reset: 0x008B, Name: MMD2_DEVS_IN_PKG1

Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present.

Table 232. Bit Descriptions for MMD2_DEVS_IN_PKG1

Bits

Bit Name

Description

Reset

Access

[15:0]

MMD2_DEVS_IN_PKG1

Vendor Specific 2 MMDs in Package 1. Clause 22 registers and PMA/PMD, PCS, and

autonegotiation MMDs are present.

0x8B

Device Address: 0x1F; Register Address: 0x0006, Reset: 0xC000, Name: MMD2_DEVS_IN_PKG2

Vendor Specific 1 and Vendor Specific 2 MMDs are present.

Table 233. Bit Descriptions for MMD2_DEVS_IN_PKG2

Bits

Bit Name

Description

Reset

Access

[15:0]

MMD2_DEVS_IN_PKG2

Vendor Specific 2 MMDs in Package 2. Vendor Specific 1 and Vendor Specific 2 MMDs are

present.

0xC000

Vendor Specific MMD 2 Status Register

Device Address: 0x1F; Register Address: 0x0008, Reset: 0x8000, Name: MMD2_STATUS

This address corresponds to the Vendor Specific MMD 2 status register.

Table 234. Bit Descriptions for MMD2_STATUS

Bits

Bit Name

Description

Reset

Access

[15:14]

MMD2_STATUS

Vendor specific 2 MMD Status.

0x2

10: device responding at this address.

11: no device responding at this address.

01: no device responding at this address.

00: no device responding at this address.

[13:0]

RESERVED

Reserved.

0x0

PHY Subsystem Interrupt Status Register

Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS

This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated

event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated

bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system.

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