MAXQ3183-RAN+ datasheet(61/102 Pages) MAXIM

61 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

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Meter Pulse

The purpose of a meter pulse is generally to advance a

mechanical counter when such a device is used as a

display. Meter pulses are also used during calibration

since time intervals can be measured with great preci-

sion.

The MAXQ3183 supports two meter pulse outputs.

These outputs can be configured for either active posi-

tive or active negative pulses by means of the POPOL

bit in the OPMODE1 register. When triggered, the pulse

goes to its active state and remains there for a period of

time defined by the PLS1_WD or PLS2_WD register,

and then returns to the inactive state (unless triggered

again).

The PLS1_WD and PLS2_WD registers contain the time

in ADC frame periods that the pulses remain in the

active state when triggered. By default, these registers

contain decimal 156 (0x9C) giving, at the default frame

rate, a pulse width of approximately 50ms.

Each pulse generator can select one parameter to be

accumulated over any combination of the three phases.

For example, one could select real energy accumulated

over all three phases for pulse output 1, and reactive

energy accumulated over all three phases for pulse

output 2. The particular parameters that can be accu-

mulated are given in the register table.

Among the quantities that can be accumulated by the

pulse subsystem are the arithmetic active energy (that

is, the accumulated positive real energy minus the

accumulated negative real energy) and the absolute

active energy (that is, accumulated positive real ener-

gy plus accumulated negative real energy). Other

quantities include RMS voltage and current, positive

and negative real energy and reactive energy in each

of the four quadrants. Select the desired accumulation

value in the QNSEL field of the PLSCFG1 and

PLSCFG2 register.

Also in the pulse configuration registers you can select

which phases to include in the accumulation. Set any or

all the PHASEA, PHASEB, and PHASEC bits in the

PLSCFG1 or PLSCFG2 registers to include them in the

accumulation.

Generating Pulses

On every DSP cycle, the MAXQ3183 adds the value in

the selected register (or set of registers) to the pulse

accumulator. If the value in the pulse accumulator

exceeds the value in the associated threshold register

(THR1 or THR2), then a pulse is started and the value in

the threshold register is subtracted from the value in the

pulse accumulator.

Meter Constant

A meter constant is the number of pulses that are gen-

erated during a standard measurement interval; for

example, a meter might specify a meter constant of

1600 pulses per kilowatt-hour. The THR1 and THR2

registers are used to specify the meter constant

according to the following formula:

In this formula, THR is the value to be written to the

threshold register, KM is the desired meter constant (in

pulses per kilowatt hour), IFS and VFS are the full-scale

voltage and current, respectively, and tFR is the frame

period in units of hours, as in the previous calculation.

As an example, assume once again a full-scale voltage

value of 558.1V = 0.5581kV, a full-scale current value of

102.4A, a desired meter constant of 1600 pulses per

kilowatt hour, and a default frame time of 360μs (88.9 x

10-9 hours). The threshold register value can be calcu-

lated as:

65,536/(1600 x 102.4 x 0.5581 x 100 x 10-9) =

7,167,174 = 0x6D5CC6

Increasing the value of the threshold register

reduces

the meter constant (that is, there are fewer pulses per

kilowatt-hour); reducing the threshold register

increases

the meter constant (that is, there are more pulses per

kilowatt-hour.)

Interrupts

The MAXQ3183 contains an interrupt subsystem to

relieve the host processor of the burden of constantly

polling the device for status. Instead, under certain cir-

cumstances, the MAXQ3183 can activate an external

pin to alert the host processor that some condition

requiring host attention has occurred.

Interrupts are managed globally by the IRQ_MASK and

IRQ_FLAG registers. In general, when a bit becomes

set in the IRQ_FLAG register, an interrupt is generated

if the corresponding bit is set in the IRQ_MASK register.

Interrupts can be configured for the following conditions:

PWRF: This flag indicates the VDVDD to the

MAXQ3183 has fallen below its nominal operating

threshold (about 2.85V). This can be taken as an

indication that power failure is imminent and that the

host processor should begin taking steps to ensure

an orderly shutdown.

CHSCH: This flag indicates that the CHKSUM regis-

ter changed its value.

THR

MFS

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