MAXQ3183-RAN+ datasheet(22/102 Pages) MAXIM

22 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Every defined register on the MAXQ3183 has a 12-bit

address (from 0 to 4095). This address is used when

addressing the register for either a read or write opera-

tion. Addresses 0 to 1023 (000h to 3FFh) are used to

address RAM registers. Registers with addresses from

1024 to 4095 (400h to FFFh) are used for virtual regis-

ters and special command registers.

Each command consists of a read/write command

code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis-

ter address, and the specified number of data bytes fol-

lowed optionally by a cyclic redundancy check (CRC).

Since SPI is a full-duplex interface, the master and

slave must both transmit the same number of bytes dur-

ing the command. When a multiple-byte register is read

or written (2/4/8 byte length), the least significant byte is

read or written first in the command.

Every transaction begins with the master sending 2

bytes that contain the command (read or write), the

address to access, and the number of bytes to transfer.

Every SPI peripheral must return 1 byte for every byte it

receives. If the master is reading 1 or more bytes from

the MAXQ3183, it must send dummy bytes during the

cycles when it is receiving a multibyte response to a

request, meeting the “send a byte to get a byte” require-

ment. But the MAXQ3183 could require time to calculate

the result, and thus might not have it ready when the

master sends the dummy byte. For this reason, the

MAXQ3183 always sends zero or more bytes of a NAK

character (0x4E or ASCII ‘N’) followed by an ACK char-

acter (0x41, or ASCII ‘A’) before sending the data.

If the master is writing 1 or more bytes, it sends the

data to be written immediately after sending the com-

mand. The MAXQ3183 returns ACK (0x41) for each

data byte. It then returns NAK (0x4E) until the write

cycle is complete, after which it returns a final ACK.

Immediately after the final ACK, the MAXQ3183 is

ready to begin the next transaction; there is no need to

wait for any other event. It is not even necessary to tog-

gle SSEL to begin the next transaction. The MAXQ3183

knows that the first transaction is over and is ready for

the next.

If, for whatever reason, it is necessary to reset the com-

munications between the host and the MAXQ3183 (for

Table 1. Command Format for SPI Register Read

BYTE

TRANSFERS

BIT

DESCRIPTION

7:6

Command Code:

00 Read

01 Reserved

10 Write

11 Reserved

5:4

Data Length:

00 1 Byte

01 2 Bytes

10 4 Bytes

11 8 Bytes

1st byte

Master sends command;

Slave sends 0xC1 byte

3:0

MSB portion of data address.

2nd byte

Master sends address;

Slave sends 0xC2 byte

7:0

LSB portion of data address.

Sync bytes

Master sends dummy;

Slave sends ACK (0x41) or

NACK (0x4E) byte

7:0

Master sends dummy byte; Slave responds with NACK if busy,

or with ACK when processing complete.

Master must receive ACK, then receive data.

3rd byte

(1st data byte)

Master sends dummy;

Slave sends data

7:0

Data, LSB

...

Nth byte

(Last data byte)

Master sends dummy;

Slave sends data

7:0

Data, MSB

(N + 1) byte

Master sends dummy;

Slave sends CRC

7:0

Optional CRC

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