MAXQ3183-RAN+ datasheet(41/102 Pages) MAXIM

41 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Current Vector Sum Threshold (ISUMLVL) (0x054)

This register specifies the threshold value for the vector sum (of three phase currents or three phase currents plus

the neutral current, configurable in the AUX_CFG register) as a fraction of the full-scale current. When the vector sum

(RMS) value exceeds this threshold value in one DSP cycle, the ISUMOVF flag in the IRQ_FLAG register is set. If the

IRQ_MASK.EISUM bit is set, the interrupt pin is driven active. The host must clear the interrupt flag. Full scale is rep-

resented by 0x10000. The maximum value allowed is 0xFFFF.

Phase Status Registers

Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C)

The X.FLAGS register contains condition flags that relate to the function of phase X (A/B/C) measurements. Once

set, these bits can be cleared only by the host.

Bit:

Name:

—

DCHRF

DCHAF

NOZXF

UVF

OVF

OCF

Reset:

BIT

NAME

FUNCTION

7:6

—

Reserved.

DCHRF

Reactive Energy Direction Change. Set when the direction of reactive power flow changes (from

capacitive to inductive or from inductive to capacitive). If the DCHRM bit is set, this bit sets the DCHR

flag in the IRQ_FLAG register.

DCHAF

Real Energy Direction Change. Set when the direction of real power flow changes (from toward the load

to toward the line, or from toward the line to toward the load). If the DCHAM bit is set, this bit sets the

DCHA flag in the IRQ_FLAG register.

NOZXF

No-Zero Crossing. Set when the voltage waveform in phase X fails to exhibit a zero crossing during one

DSP cycle. If the NOZXM bit is set, this bit sets the NOZX flag in the IRQ_FLAG register.

UVF

Undervoltage. Set when the RMS voltage in phase X falls below the undervoltage threshold set in

UVLVL. If the UVM bit is set, this bit sets the UV flag in the IRQ_FLAG register.

OVF

Overvoltage. Set when the RMS voltage in phase X exceeds the overvoltage threshold set in OVLVL. If

the OVM bit is set, this bit sets the OV flag in the IRQ_FLAG register.

OCF

Overcurrent. Set when the RMS current in phase X exceeds the overcurrent threshold set in OCLVL. If

the OCM bit is set, this bit sets the OC flag in the IRQ_FLAG register.

Bit:

Name:

Vector Sum Threshold High Byte

Reset:

0xFF

Bit:

Name:

Vector Sum Threshold Low Byte

Reset:

0xFF

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