MAXQ3183-RAN+ datasheet(23/102 Pages) MAXIM

23 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Table 2. Command Format for SPI Register Write

BYTE

TRANSFERS

BIT

DESCRIPTION

7:6

Command code:

00 Read

01 Reserved

10 Write

11 Reserved

5:4

Data Length:

00 1 Byte

01 2 Bytes

10 4 Bytes

11 8 Bytes

1st byte

Master sends command;

Slave sends 0xC1 byte

3:0

MSB portion of data address.

2nd byte

Master sends address;

Slave sends 0xC2 byte

7:0

LSB portion of data address.

3rd byte

(1st data byte)

Master sends data;

Slave sends ACK (0x41)

7:0

Data, LSB

...

Nth byte

(Last data byte)

Master sends data;

Slave sends ACK (0x41)

7:0

Data, MSB

(N + 1) byte

Master sends CRC;

Slave sends ACK (0x41)

7:0

Optional CRC

Sync bytes

Master sends dummy;

Slave sends ACK (0x41) or

NACK (0x4E) byte

7:0

Master sends dummy byte; Slave responds with NACK if busy,

or with ACK when processing complete.

Master must receive ACK before starting the next transaction.

example, if synchronization is lost), the host only needs

to wait for the SPI to time out before restarting commu-

nication from the first command byte. SPI timeout count

starts after receiving the first command byte from the

master (after the 8th SPI clock of the first byte). The

count stops and clears after receiving the last byte of a

transaction (after the 8th SPI clock of the last byte).

If the timeout count expires (exceeds COM_TIMO)

before the transaction completes, the MAXQ3183 aban-

dons the unfinished transaction and resets the SPI logic

to be ready for the next transaction. The default SPI

timeout is 360ms.

Optionally, a CRC byte can be appended to each

transaction. For write commands, the CRC byte is sent

by the master, and for read commands the CRC byte is

sent by the MAXQ3183. The CRC mode is enabled

when the CRCEN bit is set to 1 in OPMODE1 register.

Otherwise, the MAXQ3183 assumes no CRC byte is

used. The 8-bit CRC is calculated for all bytes in a

transaction, from the first command byte sent by the

master through the last data byte excluding sync bytes,

using the polynomial P = x8 + x5 + x4 + 1. If the trans-

mitted CRC byte does not match the calculated CRC

byte (for a write command), the MAXQ3183 ignores the

command.

The length of the transfer is defined by the first com-

mand byte and the status of the CRCEN bit in the

OPMODE1 register. There is no special synchronization

mechanism provided in this simple protocol. Therefore,

the master is responsible for sending/receiving the cor-

rect number of bytes. If the master mistakenly sends

more bytes than are required by the current command,

the extra bytes are either ignored (if the MAXQ3183 is

busy processing the previous command) or are inter-

preted as the beginning of a new command. If the mas-

ter sends fewer bytes than are required by the current

command, the MAXQ3183 waits for SPI timeout, then

drops the transaction and resets the communication

channel. The duration of the timeout can be configured

through the COM_TIMO register.

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