MAXQ3183-RAN+ datasheet(84/102 Pages) MAXIM

84 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Hardware Mirror Registers

ADC Configuration (R_ACFG) (0x04C)

This register is a mirror of a CPU register in the MAXQ3183. This register should not be modified by supervisory

code.

ADC Conversion Rate (R_ADCRATE) (0x04E)

This register specifies the number of system clock cycles between consecutive ADC conversions. It defaults to

0x167 (359 decimal), which specifies 360 CPU clock cycles between conversions. This register is a mirror of a CPU

Bit:

Name:

ADCASD

ADCRY

ADCCD

ADCBY

ADCIE

ARBE

ADCE

Reset:

0x0

BIT

NAME

FUNCTION

ADCASD

Disable ADC Automatic Shutdown. Normally, the ADC analog section is powered off following a

conversion to conserve power. If this bit is set, the ADC leaves the analog section powered on

following a conversion.

ADCRY

ADC Data Ready. When a conversion is complete, this bit is set to indicate that data is available. This

bit generates an interrupt if ADCIE is set.

5:4

ADCCD

ADC Clock Divider. Sets the division ratio between the CPU master and ADC clock.

00 = divide by 1

01 = divide by 2

10 = divide by 4

11 = reserved

ADCBY

ADC Busy. When set, a single ADC conversion cycle is in progress. The bit is cleared on the

conclusion of the conversion cycle.

ADCIE

ADC Interrupt Enable. If set, the ADC interrupts the CPU at the completion of a conversion cycle.

ARBE

Reference Buffer Enable. If set, the reference buffer is enabled to drive the REFO pin.

ADCE

ADC Enable. If set, the ADC hardware is activated.

Bit:

Name:

ADC Conversion Rate High Byte

Reset:

—

Bit:

Name:

ADC Conversion Rate Low Byte

Reset:

0x67

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