MAXQ3183-RAN+ datasheet(19/102 Pages) MAXIM

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Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

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for system execution, a crystal warmup timer must

count 65,536 cycles of the high-frequency clock. While

this warmup time period is in effect, execution contin-

ues using the internal 1MHz oscillator. Once the

65,536-cycle count completes (which requires approxi-

mately 8.2ms at 8MHz), the device automatically

switches over to the high-frequency clock. This crystal

warmup timer is also activated upon exit from Stop

Mode, since the high-frequency crystal oscillator is shut

down during Stop Mode.

External High-Frequency Clock

Instead of using a crystal oscillator to generate the

high-frequency clock, it is also possible to input a high-

frequency clock that has been generated by another

source (such as a digital oscillator IC) directly into the

XTAL1 pin of the MAXQ3183.

To use an external high-frequency clock as the system

clock source, the XTAL1 pin should be used as the

clock input and the XTAL2 pin should be left uncon-

nected. The master should also shut down the internal

crystal oscillator circuit by setting the EXTCLK bit

(OPMODE0.4) to 1. This bit is only cleared by the

MAXQ3183 if a power-on or brownout reset occurs and

is unaffected by other resets.

When using an external high-frequency clock, the clock

signal should be generated by a CMOS driver. If the

clock driver is a TTL gate, its output must be connected

to DVDD through a pullup resistor to ensure that the

correct logic levels are generated. To minimize system

noise in the clock circuitry, the external clock source

must meet the maximum rise and fall times and the

minimum high and low times specified for the clock

source in the

Electrical Characteristics table.

Internal RC Oscillator

When the external high-frequency crystal is warming

up, or when the MAXQ3183 is placed into LOWPM

mode, the system clock is sourced from an internal RC

oscillator. This internal oscillator is designed to provide

the system approximately 1MHz, although the exact

frequency varies over temperature and supply voltage.

If no external crystal circuit or high-frequency clock will

be used, the MAXQ3183 can be forced to operate infi-

nitely from the internal oscillator by grounding XTAL1.

This ensures that the crystal warmup count never com-

pletes, so the MAXQ3183 runs from the internal oscilla-

tor in all active modes.

Master Communications

Before the MAXQ3183 can begin performing electric-

metering operations, the master must initialize a num-

ber of configuration parameters. Since the MAXQ3183

does not contain internal nonvolatile memory, these

parameters (stored in internal registers) must be set by

the master each time a power-up or reset cycle occurs,

or each time a switch is made between LOWPM Mode

and Run Mode.

The external master communicates with the MAXQ3183

over a standard SPI bus, using commands to read and

write values to internal registers on the MAXQ3183.

These registers include, among many other items:

• Operating mode settings (Stop Mode, LOWPM

Mode, external clock mode, etc.)

• Status and interrupt flags (power-supply failure, over-

current/overvoltage detection, etc.)

• Masking control for interrupts to determine which

conditions cause IRQ to be driven low

• Configuration settings for analog channel scanning

• Power pulse output configuration

• Filter coefficients and configuration

• Read-only registers containing accumulated power

and energy data

As the MAXQ3183 obtains voltage and current mea-

surements in Run Mode or LOWPM Mode, it accumu-

lates, filters, and performs a number of calculations on

the collected data. Many of these operations (including

the various filtering stages) are configured by settings

in registers written by the master. The output results

can then be read by the master from various read-only

registers in parallel with the ongoing measurement and

processing operations.

SPI Communications Rate and Format

The SPI is an interdevice bus protocol that provides

fast, synchronous, full-duplex communications between

a designated master device and one or more slave

devices. In a MAXQ3183-based design, the

MAXQ3183 would be the slave device connected to a

designated master microcontroller.

The external master initiates all communications trans-

fers. The interrupt request line IRQ, while not technical-

ly part of the SPI bus interface, is also used for

master/slave communications because it allows the

MAXQ3183 to notify the master that an interrupt condi-

tion exists. Some SPI peripherals sacrifice speed in

favor of simulating a half-duplex operation. This is not

the case with the MAXQ3183; it is truly a full-duplex SPI

slave.

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