MAXQ3183-RAN+ datasheet(29/102 Pages) MAXIM

29 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Operating Mode Register 1 (OPMODE1) (0x002)

BIT

NAME

FUNCTION

7:4, 1:0

—

Reserved.

CRCEN

If set, a 1-byte CRC is appended to the end of each SPI read and is expected at the end of each SPI

write. See the SPI Communications Protocol section for details about how to use the CRC byte for error

checking on the SPI bus.

POPOL

This bit sets the polarity of the output pulse generators. If clear, the pulse outputs are active low; that

is, they remain in the high state until a pulse event occurs, at which time they switch low for one

pulse-width interval before reverting to the high state. If set, the pulse outputs are active high; that is,

they remain in the low state until a pulse event occurs, at which time they switch to the high state for

one pulse-width interval before reverting to the low state.

Bit:

Name:

—

CRCEN

POPOL

—

Reset:

Operating Mode Register 0 (OPMODE0) (0x001)

BIT

NAME

FUNCTION

7:5, 0

—

Reserved.

EXTCLK

When set, the high-frequency crystal oscillator is disabled and the XTAL1 pin is configured to be a

clock input for the device. This is used when it is desired to operate multiple devices from the same

clock source for purposes of maintaining synchronization.

SWRES

When set, forces the internal software to restart from the reset vector. This has the same effect as a

power-on reset, but does not specifically reset any hardware peripherals. This bit is automatically

cleared after the reset.

DSPDIS

When set, disables the signal processing software routines. The CPU continues to run at full speed,

but only to perform supervisory functions (such as servicing the SPI port).

LOWPM

When set, causes the CPU to switch its clock source from the external crystal to an internal ring oscillator

that operates at a nominal frequency of 1MHz. In this mode, the CPU continues to run, but the host must

reconfigure the parameters configured for crystal operation (such as filter settings, timeouts, and pulse

widths).

Bit:

Name:

—

EXTCLK

SWRES

DSPDIS

LOWPM

—

Reset:

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