ADIN2111CCPZ-R7 datasheet(124/125 Pages) AD

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Data Sheet

ADIN2111

PCB LAYOUT RECOMMENDATIONS

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Rev. 0 | 124 of 125

LAND PATTERN

The LFCSP has an exposed pad underneath the package that

must be soldered to the PCB ground for mechanical, electrical, and

thermal reasons.

For thermal impedance performance and to maximize heat transfer

to the PCB, the use of a 4 × 4 array of thermal vias beneath

the exposed ground pad is recommended. Via tenting is also

recommended.

COMPONENT PLACEMENT AND ROUTING

Prioritization of the critical traces and components helps simplify

the routing exercise. Place and orient the critical traces and compo-

nents first to ensure an effective layout. The critical components are

the crystal and load capacitors, the CEXT_2, CEXT_3, CEXT_6,

and CEXT_7 capacitors, and all bypass capacitors local to the

ADIN2111 device. Prioritize these components for placement and

routing, as follows:

►

Place the decoupling capacitor as close as possible to their input

pins.

►

Minimize traces turns, and use a 45° corner.

►

Avoid traces crossing power planes on adjacent layers.

►

Avoid stubs.

►

Keep the MDI traces (P1_TXP, P1_TXN, P2_TXP, and P2_TXN)

as short as possible.

►

Use matched length differential lines for each port with a differen-

tial impedance of 100 Ω.

►

Avoid vias on a high speed signal. Place ground vias next to the

signal vias to improve the return current path.

CRYSTAL PLACEMENT AND ROUTING

Particular attention is required on the crystal placement and routing

to ensure minimum current consumption, reduce stray capacitance,

and improve noise immunity.

Follow these recommendations:

►

Place the crystal, capacitors as close as possible to the

ADIN2111 XTAL_I/CLK_IN and XTAL_O pins.

►

Place the load capacitors close to each other.

►

Use a local GND plane (copper island) for the crystal and load

capacitors with a single point connection to the main GND.

►

Reduce parasitic capacitance by keeping the XTAL_I and

XTAL_O traces away from each other.

►

Adding a copper keepout on the layer beneath the crystal can

also reduce the parasitic capacitance.

PCB STACK

Follow these recommendations for the PCB stack:

►

Use a PCB stack with a minimum of four layers. Consider six

layers or more with external layers used as ground planes to

improve EMI issues (optional).

►

Define copper layer thickness based on the application and

power requirements.

►

Use internal layers for the power and ground planes.

►

Use external layers for the signal traces.

►

Use via stitching to improve ground and reduce EMI. The

stitching pattern and via to via gaps are defined based on the

application.

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