ADIN2111CCPZ-R7 datasheet(53/125 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 53 of 125

Table 44. Bit Descriptions for PHYID

Bits

Bit Name

Description

Reset

Access

[31:10]

OUI

Organizationally Unique Identifier (OUI) (Bits[23:2]). The 22 bits in the OUI field correspond to the 22 MSBs of

the manufacturer's assigned 24-bit OUI. The OUI is arranged into the PHYID register such that OUI, Bit 2 is

located at PHYID, Bit 31, and OUI, Bit 23 is located at PHYID, Bit 10.

0xA0EF

[9:4]

MODEL

Manufacturer's Model Number. The manufacturer's model number is used to identify the device.

0xA

[3:0]

REVISION

Manufacturer's Revision Number. The manufacturer's product revision number is used to indicate a revision

level of the device.

0x1

Supported Capabilities Register

Address: 0x02, Reset: 0x000006C3, Name: CAPABILITY

Table 45. Bit Descriptions for CAPABILITY

Bits

Bit Name

Description

Reset

Access

[31:11]

RESERVED

Reserved.

0x0

TXFCSVC

Transmit Frame Check Sequence Validation Capability. Indicates the ability to validate the FCS appended by

and received from the SPI host. When this bit is set it also indicates the ability of the MAC to be configured to

accept egress frames with padding and FCS appended by the SPI host, and send ingress frames to the SPI

host with the received FCS.

0x1

0: transmit FCS validation is not supported.

1: transmit FCS validation is supported.

IPRAC

Indirect PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI register

memory space.

0x1

0: PHY registers are not indirectly accessible.

1: PHY registers are indirectly accessible.

DPRAC

Direct PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI register

memory space.

0x0

0: PHY registers are not directly accessible.

1: PHY registers are directly accessible.

CTC

Cut Through Capability. Indicates if the MACPHY device supports cut through transfer of frames through the

MACPHY to and from the network.

0x1

0: cut through not supported.

1: cut through supported.

FTSC

Frame Time Stamp Capability. Indicates if the MACPHY device supports the capturing of IEEE 1588 time

stamps on frame receive from or transmit to the network.

0x1

1: IEEE 1588 time stamp capture on frame Tx/Rx is supported.

0: IEEE 1588 time stamp capture on frame Tx/Rx is not supported.

AIDC

Address Increment Disable Capability. Indicates if the MACPHY device supports the disabling of the automatic

post-incrementing of the register address in control command reads and writes through the AID bit in the control

command header.

0x0

Address increment disable is not supported.

This field is only used with the Open Alliance SPI protocol.

SEQC

TX Data Chunk Sequence and Retry Capability. Tx data chunk sequence and retry capability. Indicates if the

MACPHY supports monitoring the SEQ bit sent by the SPI host in the Tx data chunk header and the retry of Tx

data chunks.

0x0

This field is only used with the OPEN Alliance SPI protocol.

1: Tx data chunk sequence and retry is supported.

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