ADIN2111CCPZ-R7 datasheet(12/125 Pages) AD

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Data Sheet

ADIN2111

THEORY OF OPERATION

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Rev. 0 | 12 of 125

OVERVIEW

The ADIN2111 is a low power, low complexity Ethernet switch (LES)

with a dual port 10BASE-T1L transceiver designed for Ethernet

applications. The chip is available on a 7 mm × 7 mm, 48-lead

lead frame chip scale package (LFCSP) and includes the following

features:

►

Two Ethernet PHY cores with common analog circuitry

►

10 Mbps full duplex SPI for frame transfer and system register

control

►

MAC with support for 16 MAC addresses

►

Switch with cut through or store and forward operation

►

SPI to MDIO bridge to access the PHY registers

►

Input and output clock buffering

►

On-chip first in, first outs (FIFOs):

►

8 kB high priority reception FIFO for the SPI host port

►

8 kB low priority reception FIFO for the SPI host port

►

8 kB transmission FIFO for the two Ethernet ports

►

4 kB transmission FIFO for the SPI host

►

Hardware configuration pins

►

Configurable hardware interrupt pin

►

Four configurable LED pins for activity monitoring

Note that two different SPI protocols are supported to communicate

with the switch: a generic SPI protocol similar to protocols used in

other Analog Devices products, and the OPEN Alliance MACPHY

SPI protocol.

POWER SUPPLY DOMAINS

The ADIN2111 has five power supply domains and requires a

minimum of one supply rail. See the following power supplies:

►

AVDD_H is the analog power supply input for the analog front

end (AFE) circuitry in the ADIN2111.

►

AVDD_L is the analog supply voltage for the internal LDO cir-

cuits. AVDD_L can be connected to the AVDD_H rail in single-

supply mode, or to an alternative lower voltage rail in dual-supply

mode for lower power consumption.

►

DVDD1_1P1 and DVDD2_1P1 are the 1.1 V digital core power

supply inputs for Port 1 and Port 2 PHYs. DVDD_1P1 and

DVDD2_1P1 can operate from the internal 1.1 V LDO outputs

available on the DLDO1_1P1 and DLDO2_1P1 pins. Alterna-

tively, DVDD1_1P1 and DVDD2_1P1 can be driven from an

external 1.1 V supply for lower power consumption. Note that

DLDO1_1P1 and DLDO2_1P1 must not be connected together.

►

VDDIO is the digital power supply input for the ADIN2111 MAC

interface, MDIO, and digital inputs/outputs (I/Os). VDDIO can be

connected directly to the AVDD_L rail or to an external power

rail.

The System Level Power Management section describes various

application circuits that can be used as reference.

Single-Supply Applications

In a single-supply application, connect AVDD_H and AVDD_L to

VDDIO and connect DVDD1_1P1 to DLDO1_1P1 and DVDD2_1P1

to DLDO2_1P1. The appropriate supply voltage used depends on

the end application and cable length. A recommended circuit is

shown in the Single-Supply Configuration section.

Long Reach and Trunk/Spur Applications

The 1.0 V p-p transmit operating mode supports the spur use case

and can operate at a lower AVDD_H supply voltage of 1.8 V. This

mode supports intrinsic safety applications.

The higher transmit operating mode of 2.4 V p-p supports trunk

applications and requires a higher AVDD_H supply voltage of 3.3

V. This mode can be used for longer cable lengths in industrial

Ethernet environments with higher noise levels.

ANALOG FRONT-END

The AFE stage consists of a hybrid stage, 9-level DAC, line driver,

analog receive filter, input buffer, and ADC.

The line driver transmits the signal onto the line via the Port 1

(respectively Port 2) MDI interface pins, P1_TXP and P1_TXN

(respectively P2_TXP and P2_TXN). The hybrid stage subtracts the

transmitted signal from the received signal on the Port 1 (respec-

tively Port 2) MDI pins, thereby allowing full duplex operation on the

single-pair cable.

The received signal then passes through the analog receive filter

and reaches the input buffer before being sent to the ADC.

TWO PORT SWITCH

The ADIN2111 internal two port switch manages the traffic between

the SPI host, Port 1 PHY, and Port 2 PHY. The following modes of

operations are available for the switch:

►

Store and forward (to or from the SPI host)

►

Store and forward (port to port)

►

Cut through (port to port or SPI host to port).

The port to port traffic is set to cut through by default. To change

to store and forward operation, reset the port cut through enable bit

(PORT_CUT_THRU_EN) to 0 in the Configuration Register 2.

The switch has a table of 16 MAC addresses that are used deter-

mine where to forward frames. A configurable default operation

exists for frames with unknown destination addresses (DAs).

The switch integrates seven FIFOs with a total of 28 kB of buffer to

support the port to port and host to port traffic:

►

4 kB host to Port 1 PHY/Port 2 PHY transmit FIFO

►

4 kB Port 1 PHY to host high priority receive FIFO

►

4 kB Port 1 PHY to host low priority receive FIFO

►

4 kB Port 2 PHY to host high priority receive FIFO

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