ADIN2111CCPZ-R7 datasheet(77/125 Pages) AD

77 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 77 of 125

Minimum receive frame length in bytes.

Table 115. Bit Descriptions for P1_RX_MIN_LEN

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

P1_MIN_FRM_LEN

Minimum Frame Length on Receive.

0x40

R/W

P1 Rx Low Priority FIFO Frame Count Register

Address: 0xB8, Reset: 0x00000000, Name: P1_LO_RFC

The number of frames in the receive FIFO.

Table 116. Bit Descriptions for P1_LO_RFC

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x0

[8:0]

P1_LO_RFC

Receive Frame Count for the Low Priority FIFO. The number of frames in the Rx FIFO. Provided for debug

purposes. In store and forward mode, the host software only needs to know that there is at least one frame

available. See P1_RX_RDY.

0x0

P1 Rx High Priority FIFO Frame Count Register

Address: 0xB9, Reset: 0x00000000, Name: P1_HI_RFC

The number of frames in the receive FIFO.

Table 117. Bit Descriptions for P1_HI_RFC

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x0

[8:0]

P1_HI_RFC

Receive Frame Count for the High Priority FIFO. The number of frames in the Rx FIFO. Provided for debug

purposes. In store and forward mode, the host software only needs to know that there is at least one frame

available. See P1_RX_RDY.

0x0

P1 Low Priority Rx FIFO Valid Half Words Register

Address: 0xBA, Reset: 0x00000000, Name: P1_LO_RXSIZE

Number of valid half words (16 bits) in the low priority Rx FIFO.

Table 118. Bit Descriptions for P1_LO_RXSIZE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

P1_LO_RXSIZE

Data in the Rx FIFO. Number of half words (16 Bits).

0x0

P1 High Priority Rx FIFO Valid Half Words Register

Address: 0xBB, Reset: 0x00000000, Name: P1_HI_RXSIZE

Number of valid half words (16 bits) in the high priority Rx FIFO.

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