ADIN2111CCPZ-R7 datasheet(81/125 Pages) AD

81 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 81 of 125

P2 Rx Frames Dropped Due to Filtering Register

Address: 0xDD, Reset: 0x00000000, Name: P2_RX_DROP_FILT_CNT

Table 136. Bit Descriptions for P2_RX_DROP_FILT_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

P2_RX_DROP_FILT_CNT

Rx Frames Dropped Due to Filtering.

0x0

Frames Received on Port 2 with IFG Errors Register

Address: 0xDE, Reset: 0x00000000, Name: P2_RX_IFG_ERR_CNT

Table 137. Bit Descriptions for P2_RX_IFG_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

P2_RX_IFG_ERR_CNT

IFG Error Counter for Port 2 Received Frames.

0x0

P2 Transmit Interframe Gap Register

Address: 0xE0, Reset: 0x0000000B, Name: P2_TX_IFG

Table 138. Bit Descriptions for P2_TX_IFG

Bits

Bit Name

Description

Reset

Access

[31:8]

RESERVED

Reserved.

0x0

[7:0]

P2_TX_IFG

Interframe Gap. Generates an IFG of (P2_TX_IFG + 1) × 8 bit times between frames on Tx.

0xB

R/W

P2 MAC Loopback Enable Register

Address: 0xE3, Reset: 0x00000000, Name: P2_LOOP

Table 139. Bit Descriptions for P2_LOOP

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

P2_LOOPBACK_EN

MAC Loopback. Enable loopback on the MII to the PHY.

0x0

R/W

0: normal operation. Loopback disabled.

1: loopback enabled.

P2 CRC Check Enable on Receive Register

Address: 0xE4, Reset: 0x00000001, Name: P2_RX_CRC_EN

Table 140. Bit Descriptions for P2_RX_CRC_EN

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

P2_CRC_CHK_EN

CRC Check Enable on Receive.

0x1

R/W

P2 Receive Interframe Gap Register

Address: 0xE5, Reset: 0x0000000A, Name: P2_RX_IFG

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