ADIN2111CCPZ-R7 datasheet(78/125 Pages) AD

78 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 78 of 125

Table 119. Bit Descriptions for P1_HI_RXSIZE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

P1_HI_RXSIZE

Data in the Rx FIFO. Number of half words (16 Bits).

0x0

P1 to P2 Tx Size Register

Address: 0xBC, Reset: 0x00000000, Name: P1TOP2_TXSIZE

Number of valid half words (16 Bits) in Port 1 Tx FIFO to be transmitted to Port 2.

Table 120. Bit Descriptions for P1TOP2_TXSIZE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

P1TOP2_TXSIZE

Data in Port 1 Tx FIFO. Number of 16-bit words to transmit to Port 1.

0x0

P2 MAC Rx Frame Size Register

Address: 0xC0, Reset: 0x00000000, Name: P2_RX_FSIZE

Table 121. Bit Descriptions for P2_RX_FSIZE

Bits

Bit Name

Description

Reset

Access

[31:11]

RESERVED

Reserved.

0x0

[10:0]

P2_RX_FRM_SIZE

Receive Frame Size. The size of the frame at the head of the Rx FIFO in bytes. The size includes the

appended header. This register must be read before starting a frame transfer from a receive FIFO via

P2_RX. Only used with the generic SPI protocol.

0x0

P2 MAC Receive Register

Address: 0xC1, Reset: 0x00000000, Name: P2_RX

The receive FIFO is read via this register. It is possible to burst read data from the Rx FIFO over SPI.

Table 122. Bit Descriptions for P2_RX

Bits

Bit Name

Description

Reset

Access

[31:0]

P2_RDR

Receive Data Register. This field is only used with the generic SPI protocol. Reading this register returns the four

bytes at the top of the receive FIFO and pops these four bytes from the FIFO. The upper 8 bits contain the first

byte, the next 8 bits contain the second byte, and so on. When a complete frame is read out, no further data is

returned from the Port 2 Rx FIFOs until the P2_RX_FRM_SIZE register is read first.

0x0

P2 Rx Frame Count Register

Address: 0xD0, Reset: 0x00000000, Name: P2_RX_FRM_CNT

Table 123. Bit Descriptions for P2_RX_FRM_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

P2_RX_FRM_CNT

Rx Frame Count. This register increments for received good and bad frames.

0x0

P2 Rx Broadcast Frame Count Register

Address: 0xD1, Reset: 0x00000000, Name: P2_RX_BCAST_CNT

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