ADIN2111CCPZ-R7 datasheet(82/125 Pages) AD

82 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 82 of 125

Table 141. Bit Descriptions for P2_RX_IFG

Bits

Bit Name

Description

Reset

Access

[31:6]

RESERVED

Reserved.

0x0

[5:0]

P2_RX_IFG

Interframe Gap. The receive MAC checks that the IFG is greater than P2_RX_IFG × 8 bit times. If the received

IFG is too small, the MAC drops the received frame and asserts P2_RX_IFG_ERR. The maximum value

supported in this field is 63 decimal.

0xA

R/W

P2 Maximum Receive Frame Length Register

Address: 0xE6, Reset: 0x00000618, Name: P2_RX_MAX_LEN

Maximum receive frame length in bytes.

Table 142. Bit Descriptions for P2_RX_MAX_LEN

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

P2_MAX_FRM_LEN

Maximum Frame Length on Receive in Bytes.

0x618

R/W

P2 Minimum Receive Frame Length Register

Address: 0xE7, Reset: 0x00000040, Name: P2_RX_MIN_LEN

Minimum receive frame length in bytes.

Table 143. Bit Descriptions for P2_RX_MIN_LEN

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

P2_MIN_FRM_LEN

Minimum Frame Length on Receive in Bytes.

0x40

R/W

P2 Rx Low Priority FIFO Frame Count Register

Address: 0xE8, Reset: 0x00000000, Name: P2_LO_RFC

The number of frames in the receive FIFO.

Table 144. Bit Descriptions for P2_LO_RFC

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x0

[8:0]

P2_LO_RFC

Receive Frame Count for the Low Priority FIFO. The number of frames in the Rx FIFO. Provided for debug

purposes. In store and forward mode, the host software only needs to know that there is at least one frame

available. See P2_RX_RDY.

0x0

P2 Rx High Priority FIFO Frame Count Register

Address: 0xE9, Reset: 0x00000000, Name: P2_HI_RFC

The number of frames in the receive FIFO.

Table 145. Bit Descriptions for P2_HI_RFC

Bits

Bit Name

Description

Reset

Access

[31:9]

RESERVED

Reserved.

0x0

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