ADIN2111CCPZ-R7 datasheet(85/125 Pages) AD

85 / 125 page

Data Sheet

ADIN2111

REGISTERS

analog.com

Rev. 0 | 85 of 125

Table 156. Bit Descriptions for MI_CONTROL

Bits

Bit Name

Description

Reset

Access

MI_SFT_RST

Software Reset. The software reset bit allows a software reset cycle to be initiated. Mirrors

CRSM_SFT_RST.

0x0

R/W SC

MI_LOOPBACK

Local Loopback (PCS). The loopback bit allows the PHY loopback mode to be engaged.

Mirrors LB_PCS_EN.

0x0

R/W

MI_SPEED_SEL_LSB

MII Speed Selection LSB. See MI_SPEED_SEL_MSB.

0x0

MI_AN_EN

Autonegotiation Enable. Use the AN_FRC_MODE_EN bit to enable forced link configuration

mode. Mirrors AN_EN.

0x1

1 = enable autonegotiation.

0 = disable autonegotiation.

MI_SFT_PD

Software Power-Down. The software power-down bit allows the PHY to be placed in software

power-down mode. In this mode, most of the PHY circuitry is switched off. However, MDIO

access to all registers is still possible. The default value for this register is configurable

via the RX_DV/RX_CTL/SWPD_EN pin, which allows the PHY to be held in reset until an

appropriate software initialization has been performed. Mirrors CRSM_SFT_PD.

Pin Dependent

R/W

MI_ISOLATE

MII Isolate. This bit field allows the PHY to be isolated from the MII.

0x0

R/W

RESERVED

Reserved.

0x0

R/W SC

MI_FULL_DUPLEX

MII Full Duplex. The duplex mode register cannot be written and always reads as 1 because

the PHY is only able to operate in full duplex mode.

0x1

MI_COLTEST

MII Collision Test. The collision test bit cannot be written and always reads as 0 because the

PHY is only able to operate in full duplex mode, and does not have a collision detect MII

(COL) pin.

0x0

MI_SPEED_SEL_MSB

MII Speed Selection MSB. The speed selection MSB and LSB bits cannot be written and

always reads as 00 because the PHY is only able to operate at 10 Mbps.

0x0

MI_UNIDIR_EN

MII Unidirectional Enable. The unidirectional enable bit cannot be written and always reads

as 0 because the PHY does not have the ability to transmit data from the MII regardless of

whether it has determined that a valid link has been established.

0x0

[4:0]

RESERVED

Reserved.

0x0

MII Status Register

Address: 0x1, Reset: 0x1009, Name: MI_STATUS

This address corresponds to the MII status register specified in Clause 22.2.4.2 of Standard 802.3.

Table 157. Bit Descriptions for MI_STATUS

Bits

Bit Name

Description

Reset

Access

MI_T4_SPRT

100BASE-T4 Ability. The 100BASE-T4 ability bit always reads as 0 to indicate that the PHY

does not support this technology.

0x0

MI_FD100_SPRT

Full Duplex 100BASE-X Ability. The 100BASE-X full duplex ability bit always reads as 0 to

indicate that the PHY does not support this technology.

0x0

MI_HD100_SPRT

Half-Duplex 100BASE-X Ability. The 100BASE-X half-duplex ability bit always reads as 0 to

indicate that the PHY does not support this technology.

0x0

MI_FD10_SPRT

Full Duplex 10 Mbps Ability. The 10 Mbps full duplex ability bit indicates that the PHY

supports this technology.

0x1

MI_HD10_SPRT

Half Duplex 10 Mbps Ability. The 10 Mbps half duplex ability bit always reads as 0 to indicate

that the PHY does not support this technology.

0x0

MI_FD_T2_SPRT

Full Duplex 100BASE-T2 Ability. The 100BASE-T2 full duplex ability bits always reads as 0 to

indicate that the PHY does not support this technology.

0x0

MI_HD_T2_SPRT

Half Duplex 100BASE-T2- Ability. The 100BASE-T2 half duplex ability bit always reads as 0

to indicate that the PHY does not support this technology.

0x0

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