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ADIN2111CCPZ-R7 Folha de dados(PDF) 60 Page - Analog Devices

Nome de Peças ADIN2111CCPZ-R7
Descrição Electrónicos  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  125 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
ADIN2111
REGISTERS
analog.com
Rev. 0 | 60 of 125
Table 52. Bit Descriptions for IMASK0
Bits
Bit Name
Description
Reset
Access
8
TTSCAAM
Transmit Time Stamp Capture Available A Mask. Setting this bit to 1 prevents the Transmit Time Stamp Capture
Available A status bit in STATUS0 from asserting the footer EXST bit.
0x1
R/W
7
PHYINTM
Physical Layer Interrupt Mask. Setting this bit to 1 prevents the physical layer interrupt (PHYINT) status bit in
STATUS0 from asserting the footer EXST bit.
0x1
R/W
6
RESETCM
RESET Complete Mask. This bit is reserved as a mask for the reset complete (RESETC) status bit. This bit
is read only and always zero as the RESETC status bit is a nonmaskable interrupt that causes INT to always
assert when RESETC is set.
0x0
R
5
HDREM
Header Error Mask. Setting a 1 to this bit prevents the header error (HDRE) status bit in STATUS0 from
asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol.
0x1
R/W
4
LOFEM
Loss of Frame Error Mask. Setting a 1 to this bit prevents the loss of frame error (LOFE) status bit in STATUS0
from asserting the footer EXST bit.
0x1
R/W
3
RXBOEM
Receive Buffer Overflow Error Mask. Setting a 1 to this bit prevents the receive buffer overflow error (RXBOE)
status bit in STATUS0 from the footer EXST bit.
0x1
R/W
2
TXBUEM
Transmit Buffer Underflow Error Mask. Setting a 1 to this bit prevents the transmit buffer underflow error
(TXBUE) status bit in STATUS0 from asserting the footer EXST bit.
0x1
R/W
1
TXBOEM
Transmit Buffer Overflow Error Mask. Setting a 1 to this bit prevents the transmit buffer overflow error (TXBOE)
status bit in STATUS0 from asserting the footer EXST bit.
0x1
R/W
0
TXPEM
Transmit Protocol Error Mask. Setting a 1 to this bit prevents the transmit protocol error (TXPE) status bit in
STATUS0 from asserting INT.
0x1
R/W
Mask Bits for Driving the Interrupt Pin Register
Address: 0x0D, Reset: 0x43FA1F1A, Name: IMASK1
Table 53. Bit Descriptions for IMASK1
Bits
Bit Name
Description
Reset
Access
[31:25]
RESERVED
Reserved.
0x21
R
24
P2_TXFCSEM
Transmit Frame Check Sequence Error Mask for P2_TXFCSE.
0x1
R/W
23
P2_RX_IFG_ERR_MASK
Mask Bit for RX_IFG_ERR.
0x1
R/W
22
P2_TTSCACM
Transmit Time Stamp Capture Available C Mask.
0x1
R/W
21
P2_TTSCABM
Transmit Time Stamp Capture Available B Mask.
0x1
R/W
20
P2_TTSCAAM
Transmit Time Stamp Capture Available A Mask.
0x1
R/W
19
P2_PHYINT_MASK
Mask Bit for P2_PHYINT.
0x1
R/W
18
RESERVED
Reserved.
0x0
R
17
P2_RX_RDY_MASK
Mask Bit for P2_RX_RDY. This field is only used with the generic SPI protocol.
0x1
R/W
[16:13]
RESERVED
Reserved.
0x0
R
12
TX_ECC_ERR_MASK
Mask Bit for TXF_ECC_ERR.
0x1
R/W
11
RX_ECC_ERR_MASK
Mask Bit for RXF_ECC_ERR.
0x1
R/W
10
SPI_ERR_MASK
Mask Bit for SPI_ERR. This field is only used with the generic SPI protocol.
0x1
R/W
9
RESERVED
Reserved.
0x1
R/W
8
P1_RX_IFG_ERR_MASK
Mask Bit for RX_IFG_ERR.
0x1
R/W
[7:5]
RESERVED
Reserved.
0x0
R
4
P1_RX_RDY_MASK
Mask Bit for P1_RX_RDY. This field is only used with the generic SPI protocol.
0x1
R/W
3
TX_RDY_MASK
Mask Bit for TX_FRM_DONE. This field is only used with the generic SPI protocol.
0x1
R/W
2
RESERVED
Reserved.
0x0
R



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