ADIN2111CCPZ-R7 datasheet(120/125 Pages) AD

120 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 120 of 125

Frame Checker Undersized Frame Count Register

Device Address: 0x1F; Register Address: 0x800F, Reset: 0x0000, Name: FC_USZ_CNT

This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes.

When the receive error counter (RX_ERR_CNT) is read, the undersized frame error counter is latched, which ensures that the undersized

frame error count and the receive frame count are synchronized.

Table 244. Bit Descriptions for FC_USZ_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_USZ_CNT

Latched Copy of the Undersized Frame Error Counter.

0x0

Frame Checker Odd Nibble Frame Count Register

Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT

This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of frames in the

frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd

nibble frame count and the receive frame count are synchronized.

Table 245. Bit Descriptions for FC_ODD_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ODD_CNT

Latched Copy of the Odd Nibble Counter.

0x0

Frame Checker Odd Preamble Packet Count Register

Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT

This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of

nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which

ensures that the odd preamble packet count and the receive frame count are synchronized.

Table 246. Bit Descriptions for FC_ODD_PRE_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ODD_PRE_CNT

Latched Copy of the Odd Preamble Packet Counter.

0x0

Frame Checker False Carrier Count Register

Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT

This register is a latched copy of the false carrier events counter register. This register is a count of the number of times the bad SSD state

is entered. When the receive error counter (RX_CNT_ERR) is read, the false carrier events counter register is latched, which ensures that the

false carrier events count and the receive frame count are synchronized.

Table 247. Bit Descriptions for FC_FALSE_CARRIER_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FALSE_CARRIER_CNT

Latched Copy of the False Carrier Events Counter.

0x0

Frame Generator Enable Register

Device Address: 0x1F; Register Address: 0x8020, Reset: 0x0000, Name: FG_EN

This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame

generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (CRSM_DIAG_CLK_EN).

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