ADIN2111CCPZ-R7 datasheet(35/125 Pages) AD

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Data Sheet

ADIN2111

SWITCH SPI

analog.com

Rev. 0 | 35 of 125

OVERVIEW

The ADIN2111 register interface is via a 4-wire SPI consisting of the

following pins: SCLK, CS, SDI, and SDO/SPI_CFG0.

The possible access permissions of the registers are as follows:

►

R/W: read/write

►

R: read only

►

W: write only

►

R/W1C: read/write 1 to clear

The ADIN2111 also allows access to the PHY registers via an SPI

to MDIO master bridge. See the SPI Access to the PHY Registers

section.

The following registers have additional access permissions:

►

R LL: read only, latch low

►

R LH: read only, latch high

►

R/W SC: read/write, self clear

GENERIC SPI PROTOCOL

The generic SPI protocol is detailed in Table 26 to Table 33. The

protocol is determined by the hardware configuration pins. The

multiples of 32-bit words. Both single and burst access in multiples

of 32-bit words is supported. The MSB of the data is transmitted

first.

The R/W and TA fields are defined as follows:

►

R/W: read/write

►

0: read

►

1: write

►

TA: turn around

Burst writes and reads must be in multiples of 4 bytes. The last

word (4 bytes) written can contain between one byte and four

bytes of valid data. However, TX_FSIZE is still written with the

original frame size + 2 bytes for the frame header (see Figure

21). For example, to transmit a 65-byte frame that is prepended

with a 2-byte header, 67 is written to TX_FSIZE, but 68 bytes are

transferred over SDI. The last byte is not used.

It is possible to enable a CRC on the SPI protocol via a hardware

configuration pin on power-up. This 8-bit CRC uses the polynomial

x8 + x2 + x + 1 seeded with 0x0, and provides up to 3-bit error

detection. The 8-bit CRC is included for every control and data

transaction after the ADDR bits, and then after every 32-bit data-

word for every control transaction. There is no 8-bit CRC after each

32-bit data-word in data transactions because Ethernet frames

include their own 32-bit CRC.

Table 26. Control Write Transaction

MSB

LSB

D47

D46

D45

D44 to D32

D31 to D24

D23 to D16

D15 to D8

D7 to D0

SDI

R/W

ADDR[12:0]

DATA[31:24]

DATA[23:16]

DATA[15:8]

DATA[7:0]

Table 27. Control Read Transaction

MSB

LSB

D55

D54

D53

D52 to D40

D39 to D32

D31 to D24

D23 to D16

D15 to D8

D7 to D0

SDI

R/W

ADDR[12:0]

TA[7:0]

SDO

DATA[31:24]

DATA[23:16]

DATA[15:8]

DATA[7:0]

Table 28. Burst Write Transaction (Control or Data)

MSB

LSB

D79

D78

D77

D76 to D64

D63 to D56

D55 to D48

D47 to D40

D39 to D32

D31 to D24

D23 to D16

D15 to D8

D7 to D0

SDI 1

R/W

ADDR[12:0]

DATA0[31:24] DATA0[23:16] DATA0[15:8] DATA0[7:0]

DATA1[31:24] DATA1[23:16] DATA1[15:8]

DATA1[7:0]

Table 29. Burst Read Transaction (Control or Data)

MSB

LSB

D87 D86 D85 D84 to D72 D71 to D64 D63 to D56 D55 to D48 D47 to D40 D39 to D32 D31 to D24 D23 to D16 D15 to D8

D7 to D0

SDI

R/W ADDR[12:0] TA[7:0]

SDO

DATA0

[31:24]

DATA0

[23:16]

DATA 0

[15:8]

DATA0

[7:0]

DATA1

[31:24]

DATA1

[23:16]

DATA1

[15:8]

DATA1

[7:0]

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