ADIN2111CCPZ-R7 datasheet(46/125 Pages) AD

46 / 125 page

Data Sheet

ADIN2111

SWITCH SPI

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Rev. 0 | 46 of 125

to ensure that the counters do not roll over the last value read by

the host.

Table 40. Port 1 and Port 2 Statistics Counters

Name1

Description

Px_RX_FRM_CNT

PORT Rx frame count

Px_RX_UCAST_CNT

PORT Rx unicast frame count

Px_RX_MCAST_CNT

PORT Rx multicast frame count

Px_RX_BCAST_CNT

PORT Rx broadcast frame count

Px_RX_CRC_ERR_CNT

PORT Rx CRC errored frame count

Px_RX_ALGN_ERR_CNT

PORT Rx alignment error count

Px_RX_PHY_ERR_CNT

PORT Rx PHY error count

Px_RX_LS_ERR_CNT

PORT Rx long and short frame error count

Px_TX_FRM_CNT

PORT Tx frame count

Px_TX_UCAST_CNT

PORT Tx unicast frame count

Px_TX_MCAST_CNT

PORT Tx multicast frame count

Px_TX_BCAST_CNT

PORT Tx broadcast frame count

Px_RX_DROP_FULL_CNT

PORT Rx frames dropped due to FIFO full

Px_RX_DROP_FILT_CNT

PORT Rx frames dropped due to filtering

Px_RX_IFG_ERR_CNT

PORT Rx frames received with interframe gap

(IFG) errors

1 One set of counters for each port. X represents the port number.

Receive Drop FIFO Full Counter

Before the first byte of a received frame is written into the appro-

priate receive FIFO on Port 1 (respectively Port 2), the space

in the FIFO is checked. If there is no space for at least 256

bytes, the frame is dropped and the P1_RX_DROP_FULL_CNT

(respectively P2_RX_DROP_FULL_CNT) counter increments. If

there is space for at least 256 bytes in the FIFO, the logic

writes the frame to the receive FIFO. If the received frame

exceeds 256 bytes and the receive FIFO fills, the frame

is dropped and the P1_RX_DROP_FULL_CNT (respectively

P2_RX_DROP_FULL_CNT) counter increments.

Note that if a frame is destined for both the host and the other

port, and the frame is not forwarded in one of the destination FIFOs

because it is full, the frame is not counted as a dropped frame.

FRAME RECEIVE AND TRANSMIT ERRORS

By default, received errored frames do not generate interrupts.

These frames are dropped and counted, and the software must

monitor the statistics counters. The static random-access memory

(SRAM) error correction code (ECC) error and transmit overflow

error are reported in the error status register (ERR_STATUS).

These errors result in the INT pin asserting an interrupt, unless

an error is masked using the error status mask register (ERR_STA-

TUS_MASK). See the SRAM ECC Error section and Transmit

Overflow Error section.

SRAM ECC Error

When writing a frame to one of the ADIN2111 PHY FIFOs, the size

of the frame is inserted in a 16-bit word at the front of the frame and

written to the FIFO. A 5-bit ECC is placed alongside the size field.

When this location is read from the SRAM, the ECC is checked. If

a double bit error is detected, the RX_ECC_ERR or TX_ECC_ERR

bits of the STATUS1 register are set to 1. If a double bit error is

detected on reading a frame header from the receive FIFO, the

frame is not transmitted.

In response to an ECC error, a FIFO automatically clears. All

frames in the FIFO are lost, transmission stops, and a bad CRC is

appended to the frame that transmitted. The next frame received is

written to a FIFO.

Transmit Overflow Error

If the host attempts to write to the transmission FIFO but there is

not enough space, the host transmission FIFO overflow bit field

asserts (TXBOE). The software checks the space available in the

transmission FIFO by reading the transmission FIFO space register

(TX_SPACE) before attempting to write to it.

If this error occurs, the frame is automatically dumped, and the

software has no other requirement than to clear the TXBOE status

bit. Note that frames dropped because of a transmission FIFO

overflow are not counted in the statistics counters.

SPI ACCESS TO THE PHY REGISTERS

The ADIN2111 provides indirect access to the two PHY manage-

ment registers via the internal SPI to MDIO bridge. The eight

MDIOACCn registers in the SPI register map are used to access

the PHY management registers. Each MDIOACCn register corre-

sponds to an MDIO transaction.

The MDC default speed is 2.5 MHz. Either a 2.5 MHz or 4.166 MHz

management data clock (MDC) frequency can be selected via the

MSPEED bits in the CONFIG2 register.

The MDIO master polls the TRDONE bits of the eight MDIOACCn

registers in round robin mode. When the MDIO master detects that

one of the TRDONE fields is 0, the MDIO master starts an MDIO

transaction. When the MDIO transaction completes, the TRDONE

bits are set to 1, and the master proceeds to check the TRDONE

bits of the next MDIOACCn register.

Each of the two PHYs has a fixed MDIO PHY address, as follows:

►

PHY 1 MDIO address: 0x1

►

PHY 2 MDIO address: 0x2

Note that MDIO_DEVAD is always written with the device ID of

the register being accessed. MDIO_PRTAD is set to the respective

PHY MDIO address, and MDIO_ST is written to 0x0 for Clause 45

access (this applies to all of the following Clause 45 examples).

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