ADIN2111CCPZ-R7 datasheet(68/125 Pages) AD

68 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 68 of 125

Table 74. Bit Descriptions for HTX_OVF_FRM_CNT

Bits

Bit Name

Description

Reset

Access

[31:0]

HTX_OVF_FRM_CNT

Counts Host Tx Frames Dropped Due to FIFO Overflow.

0x0

Address of a Detected ECC Error in Memory Register

Address: 0x42, Reset: 0x00000000, Name: MECC_ERR_ADDR

Table 75. Bit Descriptions for MECC_ERR_ADDR

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

MECC_ERR_ADDR

Address of an Uncorrectable ECC Error in Memory. This is the address of the first uncorrectable ECC

error detected. That is when either RX_ECC_ERR or TX_ECC_ERR assert. When RX_ECC_ERR

and TX_ECC_ERR are cleared, the register is opened to catch the address of the next ECC error.

SRAM is 16 bits wide and this address points to a location in SRAM.

0x0

Corrected ECC Error Counters Register

Address: 0x43 to 0x49 (Increments of 1), Reset: 0x00000000, Name: CECC_ERRn

Table 76. Bit Descriptions for CECC_ERRn

Bits

Bit Name

Description

Reset

Access

[31:10]

RESERVED

Reserved.

0x0

[9:0]

CECC_ERR_CNT

Corrected ECC Error Count. The seven counters map to FIFOs is as follows:

0x0

CECC_ERR0: low priority Rx FIFO for Port 1.

CECC_ERR1: high priority Rx FIFO for Port 2.

CECC_ERR2: low priority Rx FIFO for Port 2 (LES only).

CECC_ERR3: high priority Rx FIFO for Port 2 (LES only).

CECC_ERR4: Tx FIFO from the host.

CECC_ERR5: Port 1 to Port 2 Tx FIFO (LES only).

CECC_ERR6: Port 2 to Port 1 Tx FIFO (LES only).

MAC Address Rule and DA Filter Upper 16 Bits Registers

Address: 0x50 to 0x6E (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_UPRn

Contains the upper 16 bits of a MAC address and the forwarding rules associated with the MAC address.

When writing the ADDR_FILT_x* registers, two register locations must be written in order for a given table entry.

For example to write table entry 0, the registers must be written in the following order:

1: ADDR_FILT_UPR0.

2: ADDR_FILT_LWR0.

Table 77. Bit Descriptions for ADDR_FILT_UPRn

Bits

Bit Name

Description

Reset

Access

APPLY2PORT2

Apply to Port 2.

0x0

R/W

0: do not apply to Port 2. Do not apply this table entry/rule to frames received on Port 2.

1: apply to Port 2. Apply this table entry/rule to frames received on Port 2.

APPLY2PORT1

Apply to Port 1.

0x0

R/W

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